Aldec Active Hdl 9 2 Crack 3
Grethe Presnar
Aldec, Inc. is a privately owned electronic design automation company based in Henderson, Nevada that provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies.
As a member of Accellera and IEEE Standards Association Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog). Aldec provides a hardware description language (HDL) simulation engine for other EDA tools such as Altium Designer and bundles special version of its tools with FPGA vendors software such as Lattice.[1]
Aldec was founded in 1984 by Dr. Stanley M. Hyduke.[citation needed] In 1985 the company released its first product: the MS-DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD.[citation needed] Sensing the growing popularity of Microsoft Windows, Aldec ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.[citation needed]
In 1996 Aldec signed an agreement with Xilinx that allowed distribution of the Xilinx-only version of Active-CAD under the Foundation name. While VHDL and Verilog were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and was still available as of 2020.[citation needed]
In 2000 Aldec released a high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms.[2] In 2001 ALDEC added hardware to its product line: the HES (Hardware Embedded Simulation) Platform allowing hardware acceleration of HDL simulation and incremental prototyping of hardware. 2003 marked the release of Riviera-PRO supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage).[citation needed] Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005.[citation needed] In 2006 Riviera-PRO was the first simulator supporting Open IP Encryption Initiative by Synplicity.[3]
Aldec also offers a special Student-Edition of Active-HDL, downloadable from Aldec's website. The Student-Edition has limited design capacity and some reduction of program functionality, but supports both design languages (Verilog resp. VHDL).
All these methods providing design stimuli can be combined in the same design. You can choose a method which is best suited for your specific design needs and be confident that a good balance between the time required to create simulation input and the complexity of the design verification exist.
The easiest way to create simulation stimuli is by adding the desired signals to the Waveform Editor and assigning stimulators that are available from the Stimulators option. There are several options to choose from. The following stimulator types are supported:
Typically, the Clock stimulator is used to drive clock signals. This type of the stimulator also can be applied by using the -repeat argument of the force macro command.The Clock stimulator produces a rectangular wave defined by the following parameters:
The Counter stimulator can be applied to VHDL signals of one-dimensional array types and integer types and Verilog integer registers and vectors. It produces a sequence of values that represent consecutive states of a counter. You can set the count step and direction, the time interval between consecutive counts, the initial value of the counter, and the counter type (Binary, Gray, Johnson, Circular One, and Circular Zero).
The Custom stimulator forces a signal or net with its own waveform (the waveform must already exist in the Standard Waveform Editor window before simulation). You can create the waveform manually by using editing features of the Waveform Editor. More typically, you will re-use a waveform obtained in the previous simulation run or loaded from a waveform file. Consider the following example: during the simulation, you were using a Hotkey stimulator to create a waveform on a certain signal. To re-use so created waveform during subsequent simulation runs, you should change the type of the stimulator from Hotkey to Custom after the re-initialization of the simulation.
The Formula stimulator produces a waveform defined by an expression based on a pre-defined syntax. The waveform is defined as a sequence of value-time pairs. The time argument determines the moment the stimulated signal assumes the value defined by the value parameter. In addition, a formula can include the -repeat argument which cause that the sequence is repeated with the specified period.
A Hotkey stimulator is similar in concept to a value stimulator but it provides a convenient mechanism for changing the forced value. To change the stimulator value, you have to simply press a specific key. Pressing the key usually toggles between two signal values, for example, '0' and '1'. However, you can define a longer list of values that will be sequentially switched by the hotkey.
A Predefined stimulator is either a clock- or formula-based stimulator to which a unique name has been assigned. Since the stimulator can be referenced by its name, you can easily assign it to several signals without repeating its definition each time.
The Random stimulator is based on the random numbers generator. It returns integer values distributed according to standard probabilistic functions. The following functions of distribution are available:
A Value stimulator drives the signal with a constant value. If you advance simulation step by step, you can change the value between steps by redefining the stimulator. This type of the stimulator also can be applied by using the force macro command.
The Waveform Editor allows you to graphically edit any waveform by using dragging, copying, pasting and drawing new waveform signals. These waveforms can be used as custom stimulators by assigning them to the desired signals.Graphically edited waveforms can also be used as simulation input in conjunction with the TestBench Wizard, described later in this document, which generates a VHDL or Verilog test program that is based on the edited waveforms.
Waveform Editor also allows comparison of the simulation results. Signals for which the difference was detected are displayed in the Waveform Editor window with the red color. The icon enabling the comparison of signals is located in the upper part of the window. The previous simulation run results must be first saved in the project folder. In case of indifferences in simulation runs an appropriate message is displayed.
Active-HDL provides a macro command language for manually entering simulation commands, such as forcing signal values, assigning formulas and executing simulation steps. You can force a value on a signal at any time during simulation by entering the appropriate macro commands in the Console window. You can also use macro commands to add forced signals to the Waveform Editor, etc.
The simulation macro commands can be executed from a file, saving you time on the manual entry of every command in the Console window. Simulation macros not only can force input signals but they can also execute other commands in the Active-HDL environment. This allows complete automation of the design verification process, particularly when combined with other simulation entry methods. For example, you can write a script to run a number of simulations using several TestBench files, one after another. Macro scripts can execute external programs such as a synthesis program, batch files, etc. You can also invoke custom commands developed in Script Basic, which are included with Active-HDL, for automation purposes.
The HDL TestBench is a VHDL or Verilog program that describes simulation inputs in standard HDL language. There are a variety of VHDL or Verilog specific functions and language constructs designed to create simulation inputs. You can read the simulation data from a text file, create separate processes driving input ports, and more. The typical way to create a TestBench is to create an additional VHDL or Verilog file for the design that treats your actual VHDL or Verilog design as a component (Unit Under Test) and assigns specific values to this component input ports.
The HDL TestBench can provide simulation inputs and also test the design outputs. For example, you can create a VHDL or Verilog program that writes design outputs to a text file and compares it against a reference file having the expected values. This methodology provides the most robust design verification with minimum user interaction.
Creating TestBenches is a tedious process. The TestBench wizard automates this process by guiding you through the process. First, it asks you to select the top level design entity to be tested. Next, you need to enter the name of the waveform file with the desired input and output ports. After answering a few additional questions, the TestBench wizard gathers the necessary information and creates a template for the test program. You can edit the wizard-generated file; adding your own test scenario and additional inputs, if required.
The TestBench wizard allows you to create a template compliant with the IEEE WAVES 1029.1 specification. WAVES is a specification for creating TestBench files in the VHDL language. It describes simulation inputs with a specific language implemented as a set of VHDL libraries. It supports verification and testing of hardware designs at any level of abstraction. You do not have to be familiar with the WAVES specification to create these files. If you select this option, the TestBench Wizard will automatically format your TestBench program using the WAVES specification. The main benefit of using this format is the ability to format simulation input and output files so that they can be used interchangeably between various simulators. The WAVES format also contains some very useful high level functions for comparing simulation outputs without writing a lot of VHDL code. The standard TestBench functions are provided in a compiled WAVES library and allow reading and writing of TestBench files in the WAVES format.
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