Altera Quartus

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Carri Seargent

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Aug 3, 2024, 5:49:28 PM8/3/24

to gapekindjolg

Here is my problem. After connecting the USB Blaster to my Win7 computer for the first time and installing the driver from altera\11.1sp2\quartus\drivers, the USB Blaster shows up in the control panel as "USB-Blaster(Altera)" but Quartus II doesn't show it in the Programmer's Hardware Setup page.

In troubleshooting, I also tried installing the same version of Quartus II and the USB blaster on my Win10 laptop, but the driver isn't signed for win10 so I dropped that approach. Back on the Win7 computer I tried using the command prompt to open altera\11.2sp2\quartus\bin\jtagconfig.exe and saw it read out the message "No JTAG hardware available".

On Quartus Pro 20.4, the chip programmer GUI would not see this device. I solved this by running the chip programmer GUI as administrator. Once the program launched, I could hear the typical USB connect/disconnect ding-dong sound effects from Windows. Then the device showed up in the programmer and it worked fine. In device manager, its new name was "Altera USB-Blaster II (JTAG interface)". After that, I didn't have to run the programmer as administrator to connect.

I just encountered this problem on Windows 11 64-bit. I ran the command "C:\intelFPGA_lite\22.1std\quartus\bin64>quartus_pgm.exe -l", which should list available programmers, and it said "No JTAG hardware available". I tried solutions listed here. None worked. The registry key suggested isn't there on W11 either.

Select the Hardware tab and select Properties. A new window should pop up with the General tab already selected. Select Change Settings. Again a new window should pop up with the General tab already selected. Select Update. Select

Find \quartus\drivers\ (Note 1: Your altera file is located at the location you selected when you first installed quartus. The location listed in this document is the default location) (Note 2: Stop at the drivers folder, i.e., do NOT go deeper by opening a folder within the drivers folder. This is important.) Select OK.

I don't think I had to restart, but you might have to. Try running C:\intelFPGA_lite\22.1std\quartus\bin64>quartus_pgm.exe -l again, and see if the device is listed. It was for me "1) USB-Blaster [USB-0]".

I have an FTDI based UARTUSB cable which I use to communicate with the board I am working on, I found that if I have the associated COM port open in my terminal application (SecureCRT, in my case) the USB-Blaster does NOT show up in Quartus.If I simply close the COM port the Blaster is once again available in Quartus.

The system includes a powerful built-in synthesis engine, which is used by default. It also supports use of the Altera Quartus II synthesizer within the design environment. To enable an FPGA project to utilize this synthesis tool the project synthesis option must be set to Altera Quartus II. This is done by selecting Project Project Options from the menus, clicking on the Synthesis tab and choosing Altera Quartus II from the dropdown Synthesizer list. Once this is selected, you must indicate the folder where the quartus_map binary executable file resides, using the dropdown's associated browse button (...). The Options region of the Synthesis tab will become populated with Altera Quatus II-related options. Configure these to best suit your design.

For advanced users, options that are not present on the Synthesis tab can be accessed from the DefaultScript_Quartus.Txt script file located in the \System folder of the installation. Analysis and synthesis switches must be configured in accordance with the Altera Introduction to Quartus II Manual.

Qsys uses a NoC-based interconnect to deliver higher performance systems compared to conventional bus and switch fabric architectures. To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe to DDR3 reference design built using Qsys. The reference design achieves throughput of over 1,400MB/s between a memory-mapped PCIe Gen2 x4 Endpoint and an external DDR3 memory. The design uses an automatically pipelined, NoC-based interconnect to packetize data for easier and faster transport. The reference design demonstrates how an Altera-provided PCIe IP core saves months of development time by eliminating the need to develop Transaction Layer Packet (TLP) encoding/decoding logic and by simplifying PCIe protocol interface complexity. Customers can download the reference design from the Qsys page of Altera's Web site at www.altera.com/qsys.

Qsys enables designers to develop large, scalable systems with a hierarchical design flow feature. Using hierarchy, designers can divide large FPGA designs that include a high number of IP cores or system components into smaller sub-systems. The hierarchical design flow in Qsys allows designers to easily manage each sub-system while giving them the ability to add additional sub-systems to the design with minimal impact on system performance.

Qsys delivers the highest flexibility by automatically handling the bridging between multiple interface standards. Designers leveraging Qsys can develop systems using Avalon-based, Qsys-compliant IP cores, and can add IP cores that use a different industry standard interface in the future without replacing the original IP cores. Qsys supports the open-standard Avalon interface with this release. Future releases of Qsys will support additional industry-standard interfaces, such as AMBA AXI from ARM.

Quartus II software version 11.0 provides faster board bring up through enhancements to the software's external memory interface toolkit and transceiver toolkit. New performance and monitoring capabilities in the external memory interface toolkit improves productivity by helping achieve maximum memory efficiency. The enhanced transceiver toolkit delivers an improved channel manager interface and an updated transceiver control panel, so designers can optimize their transceivers for improved signal integrity and bring their boards up faster.

Both the Subscription Edition and the free Web Edition of Quartus II software version 11.0 are now available for download. Qsys is available in both the Quartus II Subscription Edition and Web Edition software. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 14 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.

Since it may take some time for us to modify the script environment for Quartus, it would be great if you could run a quick test, provided that you have access to Quartus 17.0. The GPL release, available from our website, includes a few designs targeting Intel/Altera. For instance, you can pick the one below:

The README file of that design explicitly mentions that Quartus 16.0 is supported, so chances are the newer version 17.0 still works. It should be enough to go to that design, ensuring that Quartus is in your PATH environment variable and running

When I used newer versions of Quartus, I got the message of quartus_map not being supported, and therefore none of the above is printed. That should be a good first step to know if v17.0 is still supported.

I believe I can perform that testing this week. I was able to configure a Linux VM with the Quartus 17.0 tools, and copied over the GRLIB GPL release (latest). Based on your instructions above, it should be straightforward.

That is excellent news, much thanks to your team. I planned to try that out in the next day or two, and will still do so, as I am targeting Cyclone IV and V technology. I definitely believe this is a valuable update to the documentation, and again I still plan to test similar versions and post my results.

The problem was that we had Quartus 20.1 Pro and 20.4 Pro installed in our servers, so the design was failing. Therefore, the conclusion is that any version of Quartus Standard Edition at least up to 20.1 (we have not tested any further) is supported.

The problem was that Pro does not support Cyclone V, but I was getting misleading messages about the command quartus_map not being supported anymore. In the following link you can see which families are supported by which tool:

Glad you fixed it. I have quickly checked the documentation and am a bit puzzled about why the instructions on grlib.pdf do not mention the PATH variable - this step is usually a must. Currently It is only included in the section covering Windows / Cygwin installation.

The README file of that design explicitly mentions that Quartus 16.0 is supported, so chances are the newer version 17.0 still works. It should be enough to go to that design, ensuring that Quartus is in your PATH environment variable and running

Quartus Prime Lite and Questa can be installed with the quartus-freeAUR meta-package. This meta-package will also install device support for every supported device family. To save on disk space once the package is built, you can install only the necessary components. For example:

quartus-free-quartus requires quartus-free-devinfo, which is provided by any one of the packages with a quartus-free-devinfo- prefix. For example, install the quartus-free-devinfo-cyclonevAUR dependency if you have a Cyclone V FPGA.

Quartus II 13.0 Web Edition is "the last version to support Cyclone II and earlier FPGAs", so install quartus-free-130AUR[broken link: package not found] instead of quartus-free if support for such devices is needed. See also quartus-130AUR for the SP1 Subscription Edition.