Opp. Exclu 4 U & Ur Friends & family members........

[vinoth kumar]

Hi all.....
 
 
               How are you all....? How is your family.....?
 
               Not intrested, please ignore this....
 
               Here I pasted our dept. oriented  wanteds. If any one of your friends & family member have eligibility for this requirement, please inform me & send his/her resume to me.             

 

 

Roll	Criterion	Skill	Vertical	Job Location
Senior Physical/ASIC Design Engineer	6 yrs	Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). The Job involves handling high performance unit level integration for processor chip. Responsibilities include, floor planning, planning signal wires, pushing the data into lower level macros, physical integration of the lower level abstracts at the next higher level, timing closure, clean up signal and design integrity issues, physical verification and complete delivery of the high quality integrated unit to the chip level. Hands on exposure to timing closure techniques is a must. This role Involves working with global PD and timing leads,PD engineers and project managers in a matrix organization. Individual must have hands on PD experience with industry standard tools. Exposure to Cadence virtuoso tool will be added advantage. Candidates with Processor implementation back ground are preferred.	Dev	Bangalore

Circuit design engineer	4-8 yrs	Candidate will be responsible for circuit design and verification of high speed SerDes IP blocks.b/ Work with digital/ Analog / layout designers across various global sites, to integrate the IP block Skills and Qualifications:	Dev	Bangalore
Verification Lead	5-7 yrs	Implement verification plans to verify unit level, sub-system and core / chip level functionality. Define, architect and build a robust and re-usable verification environment for the core / chip.Solid understanding of VHDL / Verilog based RTL designs. Verification coding experience in System Verilog with OVM knowledge with good debugging expertize. Work closely with design engineers to ensure adequate functional and code coverage, and create fully random based testbench and testcases. Preference given to candidates with formal verification experience. BTech, M Tech/MS with minimum 5-7 years experience (atleast 2 yrs in a leadership role). 2 years experience with System Verilog / Vera / Specman Constrained Random test-bench knowledge.1 year experience with Assertion-Based Verification (SVA, PSL).	Dev	Bangalore

Verification Team Member

5 + Years

C++ programming skills essentil. Will contribute to the development of test plan, verification infrastructure development, verification of complex processor core functions and sign off of the design for tapeout. Will ensure adequate levels of thoroughness and quality in verification. Experience in high level verification languages like System Verilog, Specman or Vera is essential.Must have prior experience building test infrastructure and test cases using C++, System Verilog, Specman or Vera in atleast 3 projects. Must have handled the test plan development and contributed to teams doing verification of complex designson multiple projects.Must have familiarity with logic designs and micro architecture for complex chips/IPs preferably processor chip/cores.Exposure to post-silicon debug and characterization is desirable.

Dev

Bangalore

 

 

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Thanks & Regards,
Vinothkumar Ravichandran,          
Associate System Engineer - Software sevices for mainframes,
NASCO Project - ICD-10 - Online Team,
IBM India Pvt Ltd,
No.99,Prestige Towers,
Residency Road,
Bangalore-560025.
contact : +91-9663700699 for KA
              +91-9786016919 for TN