ParC

[Kevin Cameron]

Hi All,

The ParC project (http://parallel.cc) was spawned out of frustration with the SystemVerilog standard, and is a (working) demo for how to do a lot of the same stuff as a thin layer over C++. Unfortunately I was unaware of LLVM when I started, so it's a standalone effort rather than a sub-project of that.

Recent developments with Intel/Altera and Xilinx FPGAs with decent CPUs make ParC a more viable approach for just doing parallel programming, so if anyone wants to develop it for that do let me know.

The longer term plan is to develop a SV/VHDL/Verilog-AMS translators to ParC and then do the hard work in the C++ tools (Gcc/LLVM)  since that is a larger community.

Kev.

[Steve Hoover]

Kevin,

Please keep me posted about any progress w/ SV/VHDL/Verilog-AMS translators.  I'd very much like to develop a SV->TL-Verilog (tl-x.org) translator (and VHDL->TL-VHDL), though I haven't been able to prioritize it yet.  The first step is to identify an appropriate SV parser to start from.  Verific is probably the obvious choice ($$).  Verilator is open source, but I haven't opened the hood.  Others???

-Steve

[Erik Jessen]

Steve,

I'd take sveditor (open-source) and use it as the base for parsing SV.

http://sveditor.sourceforge.net/

Matthew Ballance is *amazing*.  File a bug, and usually there's a patch by that night.

I don't know if he plans to support AMS - but if you wanted a place to start - a very powerful, in-active-use SV editor would be a great place to start.

My personal recommendation: I'd not do translators of VHDL<->SV.  There's always problems with subtle interpretations.

I'd recommend using sveditor to parse the SV, then have an interative dialog with the user to identify bundles of signals (IP-XACT interfaces).

At that point, one can then re-output the original code, but with SV interfaces.  Which is a required prerequisite for UVM.

So - you get useful info (IP-XACT database) on the road to building a UVM testbench.

Erik

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