Xyce for everything!

[Kevin Cameron]

Hi All,

I was wondering if anybody is using Xyce in their design/verification flows?

  https://xyce.sandia.gov/

I'm interested in finding people that would like to use it for large AMS simulations (e.g. IoT SoC), or anyone interested in chasing down CDC errors with this technique -

  ICCAD-2014.pdf

A friend is looking at doing AMS simulation with Xyce using (say) Verilator for handling RTL models, if anyone wants to get involved let me know. I'd be shooting for C++ test-benches, and Xyce/Verilator for DUT.

NB: Analog simulators are not (necessarily) slow, it depends on the models used - block-level analog model behavioral models can go fast, and "real number" modeling of digital circuits provides better verification of power-managed designs (VCS/NC/Modelsim can't do power).

All the HDL standards efforts (SV-DC, SV-AMS) seem to be stymied by their closed-shops not having the expertise to build AMS solutions, and single-simulator solutions don't fit with the revenue-from-licences model the BigEDA companies use.

Kev.
https://www.linkedin.com/in/kevcameron/
PS: if you are in an IEEE-SA member company, let me know and we can also fix the standards ;-)

[Olof Kindgren]

Hi Kevin,

Have you considered looking at MAGIC? http://opencircuitdesign.com/magic/ You can find a presentation of MAGIC from ORConf last year on the FOSSi Foundation YouTube channel

//Olof

[Kevin Cameron]

Yes I have worked with MAGIC, but it is a bit brain-dead. Open-source projects really need to be trying to get ahead of the commercial stuff rather than replicating old versions of it. Xyce was built by Sandia Labs because there was no commercial tool capable of doing what they needed.

E.g. I can respin this HDL replacement project as something for neural network modeling, and I'm sure I'll get more interest than saying I'm doing a free version of (say) VCS -

http://parallel.cc

Kev.

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[Olof Kindgren]

I see your point, but I believe we need both. I haven't enough domain experience to comment on the usability of different ASIC backend tools, but my goto example for HDL simulation is Icarus Verilog and Verilator. Icarus is useful for simulating existing code bases and testbenches together with verilog models of external peripheral models while verilator is an innovative tool that is incredibly useful for clock synchronous core logic.

[Kevin Cameron]

My current plan is to build something with Xyce using Icarus/Verilator
for digital for a full mixed-signal solution, extra modelling/glue in
C++/ParC. I can make money out of that since I own the CDC detection
approach. I work on the standards committees for Verilog-AMS and
SystemVerilog, and there's no unified language dropping out of that
any time soon, so might as well just do it in open-source whatever way
works.

The real opportunity for FOSS is to get beyond RTL and do asynchronous
specifications - that should be a lot easier and faster than the
current flows, and matches what's happening in AI better.

Kev.

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