On Sat, Jan 2, 2016 at 7:27 PM, Ouabache Designworks <z3qm...@gmail.com
> I would like to start a discussion on IP-Xact and how it should fit into
> Freecellera's plan
> to conquer the world. Back around 2005 several companies joined together to
> form the spirit
> consortium in order to create a packaging standard for IP. They started with
> some work that
> Mentor had done and began to create the IP-Xact standard. They merged into
> Accellera and
> released the IEEE 1685 standard in 2009 and again in 2014.
At the risk of showing my ignorance, I'm going to reply to this.
First of all, thanks for the background and history. I have come
across IP-XACT a few times, but only briefly. It was always presented
to me as a way to specify something bog-standard (usually registers)
in XML and then have a tool generate code (verilog, vhdl, c, c++,
etc.) and documentation (word, html, pdf, etc.) from that XML.
"Packaging IP" was never mentioned to me.
> This standard was sorely needed in our industry. It tells the IP creators
> exactly how to
> package their code for delivery to their customers.
It's not clear to me what packaging means here. I don't think you
mean like, should we use a zip file, or a tar.gz?
Also, I think now is a good time for me to request that we, as the
Freecellera group, remove "IP" from our vocabulary. Look at the
explanations of IP-XACT from Acellera and from Wikipedia:
Wikipedia avoids using the ambiguous term "IP" and it is a more clear
description of what IP-XACT is.
IP stand for Intellectual Property, which is a complete misnomer in
and of itself (see: http://www.gnu.org/philosophy/not-ipr.en.html
but we in the chip design world don't even use that misnomer the same
way everyone else in the world uses it. Most everyone means "my
patented or copyrighted or trademark protected thing (that you are
using without my permission)" when they say, "IP" and we usually
mean, simply, "design component" (whether it's legally licensed or
open source or shared between two designers within the same company).
Instead of "IP", please let's just say "design component," or
"libary," or "verilog module."
> Customers no longer need
> to sift through
> new code trying to figure out how to use it. That information is available
> in the IP-Xact files.
> This enables us to do a "plug-an-play" tool set.
> You can create a SOC builder tool so that once a piece of IP is entered into
> your design environment
> that it can automatically add it into the library of available components.
> You can select it and
> instantiate it into your IP with schematic capture. You will see a symbol
> with all ports and parameters
> that you can configure and interconnect.
Schematic capture? Is this a PCB design tool?
> When you simulate your IP then the tool flows will build all subcomponents
> and load them into the tool.
> The spirit consortium realized that nobody in this industry was ever going
> to modify any of their legacy
> code in order to be compatible with some new standard so they designed
> IP-Xact to work with any way that
> you package your IP. Put your files and directories anywhere you want and
> name them anything you like.
> IP-Xact creates new files where you can tell the tools where you put things.
> You legacy code is untouched.
> IP-Xact created a naming standard that allows any engineer to create a
> module with a name that is unique
> through out the entire industry now and into the future. If you create names
> by picking something out of
> thin air then there is a good chance that your user never see a naming
> collision. But the train wrecks
> that name collisions can cause says that we need to do better than something
> than"probably works". We
> need something that will work in all cases.
Worrying about naming collisions sounds like a problem that needs to
be solved in the HDL we use. For example, Systemverilog finally gave
us namespaces (called, packages, confusingly enough), but maybe they
are still to clunky?
> IP-Xact also restores the schematic capture data formats back to our
> industry. Back in the 70's and 80's ICs
> were designed using schematic capture tools. Schematics of instantiated
> components were saved in .sch files.
> A simply click would create a symbol for a schematic and save it in a .sym
> file that had a pointer to its
> .sch file.
> Large designs could break a schematic into multiple pages and the symbol
> into multiple symbols. You could not
> do a PCB design today if you had to create one symbol with thousands of
> pins, you have to break it up.
> We lost this in the 90's when HDL/Synthesys replaced schematic capture for
> design entry and these were all
> replaced by a single .v or .vhdl file.
> This was fine for the component designers who were doing leaf cells since
> they were treated like undividable
> blocks. But this was not good for the architects that selected,configured
> and interconnected the leaf cells.
> Having the multiple file structure gave them a lot of flexibility for
> reusing circuits in more than one design.
> The IP-Xact component file is essentially a .sym file and the design file is
> a .sch file.
Again, I'm totally lost here. Maybe because when I left college
everyone was already using HDL's. This sounds, again, like something
that our HDL should solve for us. Like properly using
I like the sound of this.
> It also has problems because it has omitted allocating space for some needed
> data items. You need some data that
> IP-Xact doesn't cover then you have to use a vendor extension. You should
> never have to use a VE for any data
> if it is impossible to build the tool without it.
This sounds extremely sane and rational as well.
> Finally IP-Xact is missing the "IP-Xact Design Handbook". Standards are
> pretty dull and really only tell you about
> the "Whats". Every standard needs some author to write a handbook that also
> tells the "Whys and Hows". Look at
> Ken Parkers Boundary Scan Handbook for a good example.
> So what should Freecellera do? My suggestions:
> 1) Use IP-Xact for all tools that we create or support. If IP does not
> support IP-Xact then someone will need to create
> the IP-Xact files. You will need to dig out that information anyway to
> configure the tool but with IP-Xact it is only
> done once.
This is not clear to me. If Freecellera, for example, creates a
verilog/vhdl mixed-language simulator, how would it use IP-XACT, and
> 2) Refactor IP-Xact into appropriate dot levels and release that as
> 3) Write the "IP-Xact Design Handbook". Somebody has to do it and we might
> as well make ourselves usefull.
I think overall I need more examples of problems and how IP-XACT
solves them. More use cases. I understand the register generation
use-case that I've seen before (because every team writes a register
generator at some point...which probably hints at a Freecellera
opportunity, by the way), and I can understand generating
HDL+documentation for other boring components in the same way. Beyond
that I (and presumably not *just* I) need help understanding the
what's and why's.