Logic simulation w/o HDL (Event driven)

18 views
Skip to first unread message

kw...@verizon.net

unread,
Aug 6, 2016, 2:22:46 PM8/6/16
to Freecellera
Simulating the logic of a design is useful in the early iterations/spins of design because it is quick and easy.

Runs in Visual Studio C# IDE/Debugger so user formatted output is allowed.

Chips have inputs, outputs, storage (FFs, memories), gates/LUTs.  Inputs and storage values are
combined logically for control and by operators for values.

There is a format/syntax for input for parsing reasons, but it is simple and concise.

If a net is used in an expression and is not assigned it is an input and can be initialized or assigned at the specified time.

A net can be an arithmetic or Boolean value:
    
Basic syntax:

initial value                                   nm : val
timed value                                  nm : val @ time                                        // time is event time
repetitive timed value                   nm : val @ time : repeat interval

named logic/Boolean node            nm ? bool expr
named value node                        nm = arith expr

\c1
\c1
clocked bool assignment              nm : bool expr ? bool expr
clocked value/expr assign            nm = val expr ? bool expr


                                                 nm : value   // init @ t = 0
                                                 nm : value @ time  // timed assign
                                                 nm : value @ time : repeat interval

                                                 nm : nm/expr ? nm/expr

                                                 nm ? expr // named ctrl node

                                                 name = value expression is arithmetic.
                                                 name ? Boolean expression evaluates to true or false.

                                                 nm : nm/expre ? expr  assign either expr or nm value if expre is true


    Clocks
        \c1?expression
        \c2?expression  If "1" acts as single phase so changes occur at leading edge of c1
        Race conditions and other glitches are masked because all the setups are made before any outputs
        are launched emulating synchronous leading/positive edge triggered mode.
        Can define a two phase clock for negative/trailing edge. C1 controls the setup of Din values
        and C2 controls the "launch" of Din to Qout
        The clock domain extends to the next clock definition.
        Multiple domains can use the same clock expression so multiple blocks of logic can be used.
        Each block operates "in parallel" with other blocks using clocks with the same expression.
        Editing in a block with more or less function detail must have the same external interface to
        the other blocks. Logic blocks within each block of logic must have unique names.
        Future use of names for blocks of logic (modules?) may allow use of blockname.regname syntax
        for name resolution.  For now just naming the outputs with similar syntax seems sufficient.
       





Reply all
Reply to author
Forward
0 new messages