language choice

[Bryan Murdock]

I've seen C# proposed a couple times now on this list as a nice
language that Feecellera tools could be built upon. We need to nip
this idea in the bud.

The primary mission of Freecellera is to free us from commercial,
proprietary tools. Using a Microsoft language does not achieve that
goal. Please do not suggest moving us from one set of proprietary
tools (from the "Big 3" EDA companies) to another (Microsoft) on this
list again.

"But Microsoft is moving more and more towards open source and C# is
an open language." Verilog, VHDL, and even Specman E are also "open"
languages. What we need are unencumbered, full-featured, Free and
Open Source *implementations* of whichever languages we are going to
use and embrace. Yes, C# has mono, but that's like saying that
Verilog has Icarus. Both are noble and well-intentioned
implementations but they are not viable competitors to the proprietary
implementations. Hence the need for a Freecellera effort.

Thanks,

Bryan

On Tue, Aug 9, 2016 at 1:09 PM, <karls...@verizon.net> wrote:
> C# and Verilog both have assignments and conditional assignments so
> formatting the source for a C# class to a Verilog module is realistic..
>
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[Puneet Goel]

On C#, I completely agree with you Brian.

I want make a pitch for D (www.dlang.org). We used it as base language for creating Vlang. For the uninitiated, Vlang is an opensource, natively compiled, multicore enabled Verification language with a UVM 1.2 port. Having coded more than a hundred thousand lines for Vlang implementation, I rate D very high for any hardware/EDA project.

Coming back to Vlang, we are working hard to achieve an important milestone. Right now, we have Vlang ported and running on ARM platforms along with a full implementation of UVM-1.2. We are in the process of implementing a demo project with Vlang based UVM testbench running on Zynq and stimulating DUT implemented on Zynq FPGA. Hoping to have it working in a month from now. The testbench already works fine; we are working on integrating it with a DUT on FPGA. Zynq primarily provides an AXI based hardware/software interface, so we have to create an AXI based wrapper on top of the design to make the stimulus reach the actual DUT. Once ready we shall be putting the whole code on Github.

For now enjoy this small video that demonstrates Vlang working on Edison and stimulating a DUT mapped to Xilinx Arty. This was created by some university interns, who worked with us. The proposal was selected for DAC university booth presentation, but unfortunately could not materialize because of denial of US visa to the students. With Zynq, everything is reduced to a single board (no jumpers). We are using Parallella board available for $99 at Amazon.

https://www.youtube.com/watch?v=BgaAP0ADcYo

Note that the testench simulation speed on Edison is a tad slower than the Verilog simulation speed we could achieve on a laptop. But then this is a very small DUT and laptop runs at 1.8GHz, while Edison clocks at 500MHz. We believe speed advantage would be good if we testbench a bigger DUT. The latest Zynq offerings from Xilinx have a Quad Core ARM Cortex A 53 clocking at 1.5 GHz. For the record, memory footprint of the running testbench is small and manageable (about 20MB, while 1GB RAM is available on the platform).

For now this is a proof of concept. We hope this can go a long way for IoT verification and verification of Hardware Accelerators. Criticism, ideas, and comments are most welcome.

Soon we shall also be sharing a Qemu/Vlang/Verilog based coverification PoC.

Regards

- Puneet

[Bryan Murdock]

What is the license situation with D these days? If I remember right,
the compiler was not open source.

Bryan

[Puneet Goel]

It is completely opensource now. Earlier the backend was under GNU license, now everything is licensed under Boost license. There is also an LLVM based implementation (that we are using now) called LDC and it is also completely opensource (boost license).

[Erik Jessen]

Bryan, you have made your points very forcefully.

To avoid offending your sensibilities or continuing to get you outraged, I'll drop out of Freecellera - I'm never going to be able to achieve and maintain the 100% level of ideological purity that you insist upon.

Best of luck.

Regards,

Erik

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[Puneet Goel]

On Wed, Aug 17, 2016 at 12:05 AM, Erik Jessen <nbje...@gmail.com> wrote:

I'm never going to be able to achieve and maintain the 100% level of ideological purity that you insist upon.

And I thought 100% purity meant GPL (even LGPL is considered a compromise).

No Erik, nobody is looking for 100% purity. We need to win this game. Please stay on. I sincerely believe this list should seek more participation and outpour of thoughts and discussions than the current level.

Regards

- Puneet

[Erik Jessen]

All it takes is one ideological crusader who's on the warpath to achieve The Perfect Way.

I've found that they're unable to control themselves, and inevitably the team disintegrates - nobody will volunteer time to help an ideologue achieve something nobody is going to use.

I wish you all the best of success, using a programming language untainted by any company or government, with libraries that are equally pure.

Erik

[karls...@verizon.net]

Sorry Bryan, I misspoke.  I am trying to get away from having to use an HDL

that must be used to create a netlist  for simulation.  I am writing a simulator

tool in C# and believe that logic design and simulation should be done before

synthesis and physical design. 

The 3 EDAs are more into synthesis, now I see the mission is new tools for

synthesis/physical design rather than simulation.  Not my ball park.

Thanks, Karl

[karls...@verizon.net]

On Tuesday, August 16, 2016 at 1:22:53 PM UTC-4, Bryan Murdock wrote:

[Bryan Murdock]

On Tue, Aug 16, 2016 at 1:32 PM, <karls...@verizon.net> wrote:
> Sorry Bryan, I misspoke. I am trying to get away from having to use an HDL
> that must be used to create a netlist for simulation. I am writing a
> simulator
> tool in C# and believe that logic design and simulation should be done
> before
> synthesis and physical design.
>
> The 3 EDAs are more into synthesis, now I see the mission is new tools for
> synthesis/physical design rather than simulation. Not my ball park.
>
> Thanks, Karl

We are not limiting ourselves to synthesis. I'm sorry if I somehow
implied that. Personally I'm most interested in simulation (my day
job is Verification
Engineer).

Bryan

[Bryan Murdock]

On Tue, Aug 16, 2016 at 1:08 PM, Erik Jessen <nbje...@gmail.com> wrote:
> All it takes is one ideological crusader who's on the warpath to achieve The
> Perfect Way.
>
> I've found that they're unable to control themselves, and inevitably the
> team disintegrates - nobody will volunteer time to help an ideologue achieve
> something nobody is going to use.
>
> I wish you all the best of success, using a programming language untainted
> by any company or government, with libraries that are equally pure.

Just in case someone is taking these accusations too seriously let me
state that I am not advocating for some perfect ideal, I am not
dictating that we will use any one particular language and I am not
looking for a language completely untainted by whatever it was Erik
said. :-) There are a multitude of programming languages that run on
every major computing platform, are widely used and supported, and
have Free and Open Source compilers/interpreters and libraries.
Microsoft languages, for example, are not among those. I'm sorry if
that sounds like I'm singling out Microsoft with some sort of personal
vendetta. I'm not trying to. If there are other proprietary and/or
single-platform languages out there let me know I'll be happy to
discourage their use equally :-)

Bryan