Openings in Xilinx Hyderabad

[Naveen Singh]

                                                                                                                                                                                                                                

 

Open positions at XHD under Hot Jobs!!
Sales		·       150396 Staff FAE Bachelors or Masters in Electrical Engineering, 7+ years of industry experience with FPGA-based architecture definition, design, and support (High Speed Serial IO, Embedded Processor, or DSP knowledge a plus), Fundamental experience with EDA tools for FPGA and ASIC designs. Experience with Vivado, ISE or Quartus required (ModelSim is a plus), Knowledge of Embedded Processor design tools such as Xilinxs IP Integrator, SDK and EDK tools, or Eclipse based software development environment is a plus, In-depth knowledge of VHDL or Verilog design for ASIC and FPGA
FDST – ICD		·        152224 Staff Design Engineer – FPGA performance validation, Bachelor’s in EE and 8+ years of experience, OR Master’s in EE plus 6+ years of experience, strong background and substantial experience in design implementation targeting FPGAs, Solid understanding of FPGA Architectures and Tools (Place & route, synthesis, timing),  Verilog/VHDL and scripting languages (TCL and PERL), Good knowledge of system architecture in various end markets (Wired/Wireless/Automotive etc) is a plus.   ·       152318 Design Engineering Manager MS in EE with 13+ yrs of experience, Verilog test benches and usage of simulation tools/debug environments, strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus. Experience with formal property checking tools such as Cadence (IEV),  Jasper  and Synopsys (Magellan) is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management. Strong understanding of different phases of ASIC and/or full custom chip development is required.
PSSA		·       150961 Staff Design Engineer Masters or Bachelors in EE, 9+ yrs of relevant experience, Good understanding of complete physical design flow. Must have gone through multiple tape out cycles, revisions and metal ECOs, Expertise with PD,STA tools (like ICC, Primetime) is a must, Relevant Course work, research,  professional experience on physical closure, floor plan, CTS, routing, timing, noise, crosstalk, electro migration, IR drop, process variations, characterization, 3D ICs, low power cmos, digital logic and circuit design, ASIC/ SOC integration.   ·       151547 Senior Director MS (EE) from reputed institute with 20+ yrs of relevant experience, development of semiconductor products. Prior experience managing the development of complex SoC products is required. The ideal candidate would have seen multiple ASIC or SoC programs through all stages of development, starting with architecture definition, development and finally ending in silicon bringup, validation and rollout to production. The candidate must have deep technical background in one of the following areas: architecture, logic design, verification or physical design.   Experience with ARM, MIPS or other processor based products is desired. The candidate must also be able to lead and drive interactions with the 3rd party IP ecosystem. The candidate must be self-driven, curious and eager to expand his or her horizons. We are looking for a motivated individual who will guide his/her team but does not hesitate to roll up his or her sleeves if needed to get some work done. Experience with latest DSM SoC/ASIC methodologies is desirable. We are looking for a leader with strong interpersonal skills, a team player and one who build strong   ·       151729 Embedded Systems Architect A minimum of 15 years’ experience in embedded software Architecture, Design and Development. Intrinsic knowledge about Open Source Linux development, the Linux kernel and drivers, bare metal/Linux application development for embedded system, and in-depth knowledge of at least two more embedded operating systems/RTOS other than Linux. Experience in architecting system software solutions for silicon devices. Expert in symmetric and asymmetric multi-processing systems, embedded hypervisors, and mixed/heterogeneous processor environments. Expert in source code management with GIT as well as other source code management systems. Experience with system emulation environments and virtual development environments including QEMU. You factor agile and test driven development into your architecture. You consider verification and documentation as integral parts of architecture and rely on automated regression testing as an integral part of the overall solution.    ·       151765 Director Master’s degree in Electrical Engineering or Computer Science, at least 18 years of experience in the development of semiconductor products. Prior experience managing the development of complex SoC products is required. The ideal candidate would have seen multiple ASIC or SoC programs through all stages of development, starting with architecture definition, development and finally ending in silicon bringup, validation and rollout to production. The candidate must have deep technical background in architecture and  logic design.   Experience with Video codecs or  ARM, MIPS or other processor based products is desired. The candidate must also be able to lead and drive interactions with the 3rd party IP ecosystem. The candidate must be self-driven, curious and eager to expand his or her horizons. We are looking for a motivated individual who will guide his/her team but does not hesitate to roll up his or her sleeves if needed to get some work done. Experience with latest DSM SoC/ASIC methodologies is desirable. We are looking for a leader with strong interpersonal skills, a team player and one who build strong relationships. The ideal candidate would ideally have worked with global teams.   ·       151766 Staff Design Engineer Bachelors/Masters with 10+ yrs of relevant experience in RTL design/SoC Integration, Hands on expertise in SATA, USB3.0 protocols and design experience Knowledge in SATA, USB Serdes-phy integration is required, Work experience in ARM and AXI bus based system, knowledge of memory controller required Must be able to create synthesis constraints based on design requirements, Must  have knowledge in clock-domain crossing(CDC, Spyglass, 0in), Linting (Spyglass) and other RTL quality checks, Proficient in static timing analysis (primetime based). Have at least closed Prime time based timing closure for at least one SoC, Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis, Team player with ability to work with multisite and local teams.   ·        151818 Staff Software Engineer Bachelors/Masters in Electronics/Computer Science, 12+ years hands on DevOps with emphasis on Continuous Integration experience, Min. of 5-7 years of experience in Continuous Integration activities for Embedded platforms.  Having strong knowledge on device driver validation for Linux and Baremetal SW, Strong understanding of the principles of Continuous Delivery and Infrastructure as Code, Hands on experience on Linux SW for HW platforms, Strong knowledge on server server setups, builds and automation techniques, Programming/scripting experience in python, bash & Perl, Familiarity with version controls like Git, Github, perforce, Gerrit, Proven Experience in Integration Testing, Functional Testing and Risk Based Testing leading to high quality Embedded SW delivery.   ·        151838 Sr Staff Design Engineer Masters in EE, Should have 10+ years of experience in Physical Design Methodologies and Full Chip Design. Should have experience with methodologies like  low power designs, high frequency designs, AOCV etc. Automation skills TCL, Perl are must. Should have lead team of 6 members and well versed with Resourcing, Scheduling, Tracking, Goal Setting and Performance evaluations.   ·        152007 Sr Staff Design Engineer MS EE, 12+ years of design verification experience, 5+ years of OOP coding experience (System Verilog, OVM, UVM, SpecmanE or C++) and SV Assertions, 3+ years' experience  in a technical leadership or managerial position, Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM, Familiarity with Verilog and General Logic Design concepts, Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR3/DDR4, and peripherals such as USB and Ethernet, Strong working knowledge of UNIX environment and scripting languages such as Perl or Python, Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim, Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla, Experience in verifying multimillion gate chip designs from specifications to tape-out, Excellent communication and presentation skills.   ·        152154 Staff Design Engineer Masters in electrical or computer engineering, 8+ total of which 4+ years of experience in the verification of CPU/Video/DSP/vector processors, SIMD, etc. Experience in specifying and developing the verification infrastructure for verifying CPU/DSP/Vector-datapath designs, Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc. is a plus, Understanding of compilers and tools for DSP/Vector processors, Strong analytical problem solving, and attention to details, Strong experience in HDL, verification, and general computational logic design/verification concepts, Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc.
SIPG - IPS		·        151225 Staff Software Engineer MS in CS/EE with more than 11+ years of industry experience in development of high performance I/O subsystems using Linux, Strong development experience with linux kernel subsystem including NIC drivers and low latency, multi-threaded, high throughput PCIe SRIOV DMA drivers, Experience with virtualization (ESX, KVM, Xen etc) and networking frameworks (DPDK, ODP) etc is desired, Knowledge of datacenter networking development such as Overlay Protocols (NVGRE, VxLAN etc), Stateless Offload (RSO/TSO etc), Stateful Offload (SSL/ToE etc), Packet Processing (Tunneling, ECMP, Load Balancing etc) is desired.     ·        152189 Program Manager / Project Manager 11+ yrs of relevant industry experience with MINIMUM 6 years of program manager professional experience or equivalent engineering manager experience in high technology that covers end-to-end product lifecycle, including product definition, design, development and delivery. Ideal candidate will have excellent communication skills and a strong technical background in software and/or hardware development. MINIMUM BE or equivalent science/engineering degree; MBA is a plus   ·        151542 Staff Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 11+ years of relevant experience in IP and SOC verification, Proven end to end verification of complex IP using system verilog and any of latest methodologies which include UVM, OVM, VMM, Strong domain knowledge of latest ARM based interfaces which include AXI Memory Map and AXI streaming and high Speed serial connectivity, etc. Proficient knowledge of system verilog, HVL based methodology (UVM or OVM) and  hands on scripting experience for automation, Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage, Understanding and experience in verification of Ethernet, PCIe, Memory, MIPI, SSD, NVMe will be an added advantage, Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus.
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SIPG - IDT		·       151562 Staff Software Engineer A minimum of Bachelors in EE, CS, CE with 12 years of relevant work experience, Strong background in simulation and performance estimation methodologies. Experience in creating large scale models using SystemC TLM 2.0 is required. Experience in atleast one of the technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is required. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is required. Strong software development and debug skills, fluency in C/C++ including OOP, data structures, and algorithms is required. Experience in software development environment on Linux and/or Windows. Any exposure to compiler technologies, especially LLVM, is a big plus. Good understanding of SoC architectures and protocols like AMBA/AXI is required. Familiarity with IP based design creation flows including IP-XACT is advantageous.

 

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