Fwd: Employee Referrals : Hot Jobs

[Naveen Singh]

Please send your resume to me, if interested.                                                                                                                             

 

Open positions at XHD under Hot Jobs!!
FDST – ICD		·        152980 Staff Design Verification Engineer - FPGA SOC BS with 7+ years /MS with 5+ years/ PhD with 3+ years in Electrical Engineering, Computer Engineering, or Computer Science. Proven track record in technical leadership and management of a small team. This includes planning, execution, tracking, verification closure, and delivery to programs. Strong experience with development of UVM, OVM, VMM and/or Verilog, System Verilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus. Strong experience in full chip verification. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in modeling SystemC and using SystemC based models in verification is a plus. Experience with FPGA programming and software & Verification experience in  PCIe, Processors, Graphics is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.   ·        151840 Senior Design Verification Engineer 2 - Fullchip FPGA SOC/Sub System BS with 6+ years / MS with 4+ years /PhD with 2+ years in Electrical Engineering, Computer Engineering, or Computer Science. Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Verification Experience in protocols like AXI, DDR4,  HBM, PCIe, Processors, Graphics is a plus. Experience in block level NOC(Net work on Chip) verification , experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan), experience in modeling SYSTEMC and using SYSTEMC based models in verification, experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques and experience with FPGA programming and software is a plus.   ·        152448 Senior Design Engineer BS with 5+ yrs / MS with 3+ yrs / PhD with 1+ yrs in Electrical Engineering, Computer Engineering or Computer Science. Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs. Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience with FPGA programming and software, Verification Experience in AXI, DDR4, PCIe, Processors, Graphics and experience with one of scripting language like perl, python is a plus.   ·        151969 Senior IC Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience. 4+ years of experience in designing complex blocks of an SoC Excellent Verilog and logic design concepts. Experience with sign off tools like DC/PT. Experience with automation using scripting techniques such as PERL, Python or TCL. Knowledge of bus protocols like AXI/AHB. Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.
SIPG - IDT		·        152153 Staff Software Engineer BS/MS (PhD preferred) in CS/EE with a minimum of 8 year experience in compilers and parallel programming environments. Experience with various aspects of implementing compilers for parallel programming languages. Good understanding of programming languages and parallel programming models. Experience in implementing many of the following in production compilers: Global optimization, dependence analysis, vectorization, auto-parallelization, inter-procedural analysis and optimization, profile-feedback optimization, language front-end design and implementation, and code generation. Building a good compiler framework LLVM experience. Experience with ARM compilers is a plus, Solid understanding of machine architectures and micro-architectural performance considerations. Demonstrated C/C++ programming skills with production system software
SIPG – SVAB		·        152323 Senior Verification engineer (Platforms) BS in EC/EE/CS with 9+ years or MS with 7+ years of experience in electronic design and software development Minimum 4 years’ experience in verification/validation of complex designs, preferably in FPGA domain, with knowledge on Xilinx Tools like IP Integrator etc. Domain expertise in atleast one of: Data Center, ADAS, Video Processing applications .Strong understanding of logic design, timing constraints, timing analysis and FPGA implementation flow .Expertise in debugging using simulation (Questa/VCS/etc.) as well as on boards using debugger/scopes . Good understanding of interface protocols like DDRx/PCIe/Ethernet/USB/etc. Expertise in: Verilog, System Verilog, VHDL. Good Knowledge in Tcl, Perl, Shell etc. Domain specific expertise in Networking/Wireless/Video or similar would be beneficial.   ·        152319 Senior Software Engineer MSEE or BSEE with 4 to 5 years’ experience in FPGA/ASIC design or EDA tool support. Experience with DSP designs, Simulation, at least one of the HDLs, Digital Logic or C based synthesis or Knowledge of SimuLink and MATLAB Good knowledge of C/C++. Debug and problem solving ability.    ·        152629 Senior Hardware Validation Engineer BS in EC/EE/CS with 5+ years or MS with 3+ years of experience in electronic design and software development . Minimum 1 year experience in verification/validation of complex designs, preferably in FPGA domain, with knowledge on Xilinx Tools like IP Integrator etc. Expertise in HDL: Verilog/System Verilog/VHDL .Good understanding of logic design, timing constraints, timing analysis and FPGA implementation flow . Experience in debugging using simulation (Questa/VCS/etc.) as well as on boards using debugger/scopes . Good Knowledge in Tcl, Perl, Shell etc Protocol specific expertise such as DDR/PCIe/ Ethernet would be beneficial. Experience on NOC verification/Validation would be beneficial   ·        152115 Senior Design Engineer BS in EC/EE/CS with 9+ years or MS with 7+ years of experience in electronic design and software development. Minimum 4 years’ experience in creating and validating complex designs, preferably in FPGA domain, with knowledge on Xilinx Tools like IP Integrator etc . Strong understanding of Logic Design Concepts, timing constraints, timing analysis and FPGA implementation flow. Domain specific expertise in Networking/Wireless/Video or similar. Good understanding of interface protocols like DDRx/USB/PCIe etc. Expertise in: Verilog HDL, System Verilog, VHDL. Good Knowledge in Tcl, Perl, Shell etc
PSSA		·        152680 Senior Design Engineer BE/BTech/ME/MTech/MS (ECE/EEE) with 8+ years of design verification experience, 5+ years of OOP coding experience (System Verilog, SpecmanE or C++) and SV Assertions. Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM. Familiarity with Verilog and General Logic Design concepts. Knowledge of system-level architecture including buses like AXI/AHB and ARM based system. Well versed with concepts with digital video domain. Experience with Video CODEC based on H.265/H.264 standards. Experience with Graphics accelerator like MALI-400, MALI-622 or PowerVR. Strong working knowledge of UNIX environment and scripting languages such as Perl or TCL. Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim. Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla. Experience in verifying multimillion gate chip designs from specifications to tape-out. Excellent communication and presentation skills . Demonstrate the ability to work with cross-functional teams.
SIPG - IPS		·        152963 Senior Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 8+ years of relevant experience in IP verification and validation. Proven end to end verification of complex IP using System Verilog and latest methodologies which include UVM, OVM, VMM. Strong understanding and experience in verification of Ethernet protocols and IEEE 802.3 standards . Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc. Proficient knowledge of System Verilog, HVL based methodology (UVM or OVM) and  hands on scripting experience for automation. Experience in verification including constrained-random, coverage driven verification environments. Strong debugging, verification and board validation skills. Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage. Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus. Should have handled verification of complex RTL designs and validating them on the boards. Self-driven, motivated, result oriented individual with superior academic achievements . Excellent interpersonal, written,  group communication and problem solving  skills .   ·        152194 Senior Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/CE with at least 6+ years of experience in post silicon validation. Strong understanding of programming using C/C++ and should have working experience in driver/application development. Strong experience with debugging of failures  on target boards is must. Good organizational skills with ability to multi-task, prioritize, and track many activities. Service and results oriented . Self-driven, motivated, results oriented individual with superior academic achievements. Excellent interpersonal, written,  group communication and problem solving  skills   ·        152857 Senior Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 6+ years of relevant experience in IP and SOC verification. Proven end to end verification of complex IP using system verilog and any of latest methodologies which include UVM, OVM, VMM. Strong domain knowledge of latest ARM based interfaces which include AXI Memory Map and AXI streaming and high Speed serial connectivity, etc. Proficient knowledge of system verilog, HVL based methodology (UVM or OVM) and  hands on scripting(Perl, Tcl) experience for automation. Knowledge of FPGA architecture and working experience with Xilinx Implementation tools especially vivado IDE and system building with IPI is an added advantage. Understanding and experience in verification of Ethernet, PCIe, Memory, MIPI, SSD, NVMe, TSN will be an added advantage. Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus. Self-driven, motivated, results oriented individual with superior academic achievements. Excellent interpersonal, written,  group communication and problem solving  skills   ·        152859 Senior Design Engineer B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 6+ years of relevant experience in IP design. Proven end to end design of complex IP using Verilog. Strong understanding and experience in design of Ethernet protocols and IEEE 802.3 standards. Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc. Proficient knowledge of Verilog, HDL based methodology and hands on scripting experience for automation. Strong knowledge of digital electronics and digital systems. Strong debugging skills. Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage. Having System level knowledge / Validating IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus. Should have handled design and validation of complex RTL designs on board. Self-driven, motivated, result oriented individual with superior academic achievements. Excellent interpersonal, written, group communication and problem solving  skills   ·        152866 Senior Design Engineer 2 B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 9 + years. A major part of your responsibility will be to take a lead technical role in all phases of the product development cycle from architecture through implementation, prototyping, validation and support including: Evaluating high level architecture to a implementation feasibility leve, Be the main liaison from the IP engineering team to the high speed IO design team and be the local high speed link design expert, contribute to new process improvement in design and development methodologies that impact the productivity, Evaluating and executing design and development plans for IPs,  u-Architecture, design, documentation, prototyping, Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality. Strong logic design concepts and computer design. Expertise in Verilog, VHDL and exposure to industry simulators. Expertise in front end RTL design flow steps like lint, CDC, STA etc. Expertise in IP design. Knowledge of storage domain protocols like NVMe, SATA, PCIe, RDMA etc is desirable. Working knowledge of C, C++ languages and experience in scripting (like csh, perl)
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SIPG – FPGA Implementation		·        152875 Staff Software Engineer BS or MS in CS, EE or CE with 8+ years of software development experience. Background in EDA tools development preferred.Strong background in computer algorithms and data structures. Strong background in C++ programming including boost and STL. Familiarity with parts of the VLSI Implementation or Verification flow. Familiarity with Verilog or VHDL. Excellent problem solving skills and willingness to think outside the box. Experience with production software quality assurance practices, methodologies and procedures. Excellent communication skills and experience working with global teams. Preferred: Exposure to any of these areas: Compilers, RTL front-end development, RTL Synthesis algorithms, datapath or high-level synthesis, Timing/area/power optimizations, Technology mapping, Static timing analysis, Simulation, Formal Verification or Design For Test, Exposure to FPGAs and FPGA software tool chain.   ·        152450 Senior Software Engineer BS or MS in CS, EE or CE with 5+ years of software development experience. Background in EDA tools development preferred. Strong background in computer algorithms and data structures, especially graph algorithms. Strong background in C++ programming including boost and STL. Proficiency in scripting using Python and/or Perl. Excellent problem solving skills and willingness to think outside the box. Experience with production software quality assurance practices, methodologies and procedures. Excellent communication skills and experience working with global teams. Preferred: Exposure to any of these areas: Compilers, RTL front-end development, Exposure to FPGAs and FPGA software tool chain, VLSI Implementation or Verification flow , Familiarity with System Verilog, Verilog or VHDL, Familiarity with Java/JavaScript’s/HTML , Expertise with SQLDB or MongoDB,   ·        152701 Senior Software Engineer BS or MS in CS, EE or CE with 3+ years of software development experience. Background in EDA tools development preferred. Strong background in computer algorithms and data structures. Strong background in C++ programming including boost and STL. Familiarity with parts of the VLSI Implementation or Verification flow. Familiarity with Verilog or VHDL. Excellent problem solving skills and willingness to think outside the box. Experience with production software quality assurance practices, methodologies and procedures. Excellent communication skills and experience working with global teams. Preferred: Exposure to any of these areas: Compilers, RTL front-end development, RTL Synthesis algorithms, datapath or high-level synthesis, Timing/area/power optimizations, Technology mapping, Static timing analysis, Simulation, Formal Verification or Design For Test, Exposure to FPGAs and FPGA software tool chain.

 

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