Cellular RAM controller

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Nov 17, 2013, 2:53:53 PM11/17/13

to fpga...@googlegroups.com

hi,

I have uploaded the VHDL files for the RAM controller.

The files are not complete yet and I am still working on them...

Enjoy.

Meir

RAM_Manager_tb.vhd

read_addr_gen_tb.vhd

read_address_generator.vhd

Cell_RAM_Manager.vhd

cell_RAMManager_tb.vhd

Mem_init.vhd

Mem_init_tb.vhd

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