Conversione from BIT to XSVF

[Marco]

About a month ago i discussed about the object of the post. I think
that it maybe useful for many others users, and so i decided to re-
open the theme in a dedicated topic.
My question was: Is there a way to pass from BIT (edit by ISE) to XSVF
format without using iMPACT?
Chris anwered:

On 27 Apr, 12:25, Chris McClelland <fpgalink...@m3.ath.cx> wrote:
> I just run "make", which goes all the way from source VHDL to XSVF. It
> will work out of the box on Linux, but on Windows you need to install
> the MakeStuff build infrastructure[1].
>
> You can continue using ISE for editing if you like, but I personally
> prefer Emacs. I have also heard good things about Sigasi[2].
>
> There is a rule[3] to go from .bit to .xsvf, which just needs the XILINX
> environment variable to be set.
>
> On my Linux desktop it's set to /opt/Xilinx/13.1/ISE_DS/ISE and on my
> Windows laptop it's set to C:\Xilinx\11.1\ISE.
>
> The XSVF generation uses Xilinx iMPACT in batch mode, which needs to be
> told what devices are present on the JTAG chain. This is specified in
> the vhdl/platform/*/platform.batch files, e.g [4].
>
> On Xilinx-supported platforms (i.e Linux & Windows), for the special
> case where the device to be programmed is at the beginning or the end of
> the JTAG chain, it should be possible to query enough information from
> the JTAG chain itself to eliminate the need for the .batch files
> altogether. Unfortunately this is not practical on MacOSX, so I have not
> put any effort into it.
>
> Chris
>
> [1]http://www.makestuff.eu/wordpress/?page_id=1489
> [2]http://www.sigasi.com/screencast/quick_intro
> [3]https://github.com/makestuff/libfpgalink/blob/master/vhdl/Makefile#L59
> [4]https://github.com/makestuff/libfpgalink/blob/master/vhdl/platforms/n...
>

I've tried to look at the code indicated, but i've a question. If i
have many devices on my chain, how i can indicate that in the batch
and config files?
And, in the makefile what does it mean this fields?
MAPFLAGS = -cm area
PARFLAGS = -t 1
Thank you for each explanation.
-Marco

[Chris McClelland]

The scan-chain is specified in the .batch file in your board's platform
directory. You need a BSDL file for each device in the chain. The BSDL
file can either be found in the ISE installation or if it's a non-Xilinx
part you can create a BSDL from within the iMPACT GUI. Once you have
BSDL files for all the devices you're NOT programming, and a .bit file
for the device you ARE programing, you specify them all in the .batch
file for your board:

$ cat libfpgalink/hdl/sync/platforms/nexys2-1200/platform.batch
setMode -bs
setCable -port xsvf -file top_level.xsvf
addDevice -p 1 -file top_level.bit
addDevice -p 2 -file ${XILINX}/xcf/data/xcf04s.bsd
program -p 1
quit

This says that the Digilent Nexys2 has an FPGA and a JTAG PROM on the
chain.*

In libfpgalink/hdl/common/top.mk, each supported board defines four
macros, VENDOR, FPGA, MAPFLAGS and PARFLAGS. Generally when you start an
ISE project, you specify the FPGA family & part, and when you build your
project, ISE gives appropriate options to the programs implementing the
various stages in the process (synthesis, map, place & route, .bit
generation etc). For some reason, ISE gives different options to map and
par for spartan-3 and spartan-6 devices. I have just codified in the
Makefile what ISE does for different FPGA families. In other words, the
.bit file you get from the make build should be identical to the one you
get from the same code built in ISE (assuming default settings).

Chris

* Note that the only piece of information in the BSDL files which is
relevant is the JTAG instruction length, given by Instruction_Length. So
as long as you know that, you can just copy an existing generated BSDL
file (e.g
https://github.com/makestuff/vhdl/blob/master/test000/atmega162.bsd) and
change the value for Instruction_Length. In theory all that's needed by
the programming algorithm is the number of bits to shift each JTAG
instruction by. If there are only two devices in the chain, this can
always be determined by querying the chain itself. In theory the
programming algorithm only needs to be given offset information when
there are three or more devices in the chain AND the one you want to
program is in the middle. At some point I will add code to infer as much
information as possible about the chain, which will make this step
easier for users. I believe this will be necessary when I start
supporting multi-device boards based on Altera FPGAs anyway, because the
Altera SVF-generator appears to assume there will only ever be one
device in the chain.
-------------------------------------------------------------------------------------

On 19/05/12 12:11, Marco wrote:
> About a month ago i discussed about the object of the post. I think
> that it maybe useful for many others users, and so i decided to re-
> open the theme in a dedicated topic.
> My question was: Is there a way to pass from BIT (edit by ISE) to XSVF
> format without using iMPACT?
> Chris anwered:
>
> On 27 Apr, 12:25, Chris McClelland<fpgalink...@m3.ath.cx> wrote:
>> I just run "make", which goes all the way from source VHDL to XSVF. It
>> will work out of the box on Linux, but on Windows you need to install
>> the MakeStuff build infrastructure[1].
>>
>> You can continue using ISE for editing if you like, but I personally
>> prefer Emacs. I have also heard good things about Sigasi[2].
>>
>> There is a rule[3] to go from .bit to .xsvf, which just needs the XILINX
>> environment variable to be set.
>>
>> On my Linux desktop it's set to /opt/Xilinx/13.1/ISE_DS/ISE and on my
>> Windows laptop it's set to C:\Xilinx\11.1\ISE.
>>
>> The XSVF generation uses Xilinx iMPACT in batch mode, which needs to be
>> told what devices are present on the JTAG chain. This is specified in
>> the vhdl/platform/*/platform.batch files, e.g [4].
>>

>> On Xilinx-supported platforms (i.e Linux& Windows), for the special

[Marco]

Hi Chris, thank you very much for your reply. I've found it very
interesting. Sorry if i write just now but in the last month i've been
very busy with my job.
I'm trying to run your example in makestuff build infrastructure but i
can't do it (perhaps i'm doing something wrong with the makefile).
Please, could you post the instruction to correctly build it? And for
SP3 example?
Thank you much for everything
-Marco

[Chris McClelland]

Marco,

It would be very helpful if, when you request help for something which
does not work, you give details of exactly what you have done, and
exactly what happened when you did it. Saying "I just can't do it" does
not give me enough information to help you effectively.

I just built the synchronous VHDL ex_cksum example like this:

chris@wotan$ cd $HOME
chris@wotan$ mkdir marco
chris@wotan$ cd marco/
chris@wotan$ wget -q
http://www.swaton.ukfsn.org/bin/libfpgalink-20120507.tar.gz
chris@wotan$ tar zxf libfpgalink-20120507.tar.gz
chris@wotan$ cd libfpgalink-20120507/hdl/sync/vhdl/ex_cksum/
chris@wotan$ echo $XILINX
/opt/Xilinx/13.1/ISE_DS/ISE
chris@wotan$ echo $PATH | tr ':' '\n' | grep -i xilinx
/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64
chris@wotan$ make
:
chris@wotan$ ls -la top_level.xsvf
-rw-r--r-- 1 chris users 484126 Jun 10 14:49 top_level.xsvf

The result is an XSVF file suitable for a 1200K-gate Digilent Nexys2. If
you have a different board you will need to supply the platform when you
run "make". Supported platforms for the FX2-based boards are: "atlys",
"lx9", "nexys2-1200", "nexys2-500", "nexys3", "s3board" & "xylo-l". For
example, to build for the KNJN Xylo-L, you'd do "make PLATFORM=xylo-l".

Chris

[Marco]

Sorry, you're perfectly right. With your directive i've solved my
problem. Thank you very much Chris.

For all Windows users:
_Create a system variable XILINX containing the path of ISE (for
example: C:\Xilinx\13.2\ISE_DS\ISE)
_Then add the following variabile to the Path: %XILINX%\bin\nt
_At last, the makefile correctly run! :-)

Best Regards,
-Marco