Circuit Evolution on iCE40UP

[Brooklyn Jennings]

Hello, 
I am a student working on an iCE40UP based evolvable-hardware research project, which involves repeatedly re-configuring the FPGA fabric and then taking a measurement of some figure of merit. My research group is currently trying to figure out the lower bound of CRAM reconfiguration time, and if a partial write to some region of CRAM would be possible. From the scattered posts about benchmarks we are expecting programming time on the order of 10ms. We have the iCE40UP configured in SPI peripheral boot mode. Currently, our understanding is that the CRAM must be written serially, in its entirety with no possibility of writing only to specific sectors. Does anyone have any experience attempting similar partial reconfiguration on these FPGAs?

Also, we are looking to switch from Makefiles to manage our scripting to APIO projects, however, it seems that the APIO seems to still be under pretty significant development, is there any sort of timeline for when APIO might reach v1.0 and slow down its CLI/userspace changes?  

[charli va]

Hello! An exciting project! I hope it goes well and we look forward to hearing from you.

In principle, if you're using the current development version of Apio, there won't be many more radical changes. We're currently finishing testing to release the 1.0 release, but the release will be finalized in the coming weeks along the summer.

The new version can help you a lot because parameters have been introduced to obtain JSON outputs and facilitate integration with other systems/scripts...

We're in the midst of very important changes to all our core software. We're sorry if both Apio and IceStudio may cause you headaches in the coming months, but the effort will be worth it.

Thanks for your feedback.

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