FPGA I/O ports is not defined

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Олег Бахарев

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Sep 3, 2018, 5:41:16 AM9/3/18
to FPGAwars: explorando el lado libre
I encountered a problem: I create a project under iCEStick, I define a UART block, but when I try to build, an error appears that the ports are not defined. How to solve the problem?
DeepinScreenshot_20180903123752.png
test_uart.ice
UART_RECEIVER.ice

Juan Gonzalez Gomez

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Sep 3, 2018, 7:55:56 AM9/3/18
to FPGA-WARS: explorando el lado libre
Hi!

You have declared 8 output-pints, but 4 of them are not attached to actual pins. You, what you have to do is to assign them. For example like this:

Screenshot from 2018-09-03 13-53-52.png

I am attaching the corrected icestudio project for you to test

Best regards, Obijuan


El lun., 3 sept. 2018 a las 11:41, Олег Бахарев (<discon...@gmail.com>) escribió:
I encountered a problem: I create a project under iCEStick, I define a UART block, but when I try to build, an error appears that the ports are not defined. How to solve the problem?

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test_uart.ice

Олег Бахарев

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Sep 3, 2018, 8:51:07 AM9/3/18
to FPGAwars: explorando el lado libre
Does he scold each time when not all ports are assigned?
Thank you very much)) I ran the corrected project, though, made a small correction - removed the duplicate port D5.


понедельник, 3 сентября 2018 г., 14:55:56 UTC+3 пользователь Obijuan написал:
Hi!

You have declared 8 output-pints, but 4 of them are not attached to actual pins. You, what you have to do is to assign them. For example like this:

Screenshot from 2018-09-03 13-53-52.png

I am attaching the corrected icestudio project for you to test

Best regards, Obijuan


El lun., 3 sept. 2018 a las 11:41, Олег Бахарев (<discon...@gmail.com>) escribió:
I encountered a problem: I create a project under iCEStick, I define a UART block, but when I try to build, an error appears that the ports are not defined. How to solve the problem?

--
Has recibido este mensaje porque estás suscrito al grupo "FPGAwars: explorando el lado libre" de Grupos de Google.
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Juan Gonzalez Gomez

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Sep 3, 2018, 9:09:00 AM9/3/18
to FPGA-WARS: explorando el lado libre
El lun., 3 sept. 2018 a las 14:51, Олег Бахарев (<discon...@gmail.com>) escribió:
Does he scold each time when not all ports are assigned?

Yes. When using input or outputs (yellow boxes), they always have to be assigned to real pin


Thank you very much)) I ran the corrected project, though, made a small correction - removed the duplicate port D5.

Ups! You are right! Did not realize that there were another D5 pin :-)

 


понедельник, 3 сентября 2018 г., 14:55:56 UTC+3 пользователь Obijuan написал:
Hi!

You have declared 8 output-pints, but 4 of them are not attached to actual pins. You, what you have to do is to assign them. For example like this:

Screenshot from 2018-09-03 13-53-52.png

I am attaching the corrected icestudio project for you to test

Best regards, Obijuan


El lun., 3 sept. 2018 a las 11:41, Олег Бахарев (<discon...@gmail.com>) escribió:
I encountered a problem: I create a project under iCEStick, I define a UART block, but when I try to build, an error appears that the ports are not defined. How to solve the problem?

--
Has recibido este mensaje porque estás suscrito al grupo "FPGAwars: explorando el lado libre" de Grupos de Google.
Para cancelar la suscripción a este grupo y dejar de recibir sus mensajes, envía un correo electrónico a fpga-wars-explorando-el...@googlegroups.com.
Para publicar en este grupo, envía un correo electrónico a fpga-wars-explora...@googlegroups.com.

--
Has recibido este mensaje porque estás suscrito al grupo "FPGAwars: explorando el lado libre" de Grupos de Google.
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