Bidirection pin / data bus

[KT Chiam]

Hi,

Is there example of how to use bidirectional pin such as data bus to access parallel flash memory? There is only input port and output port in Ice Studio.

Thank you,

Best Regards,

KT

[charli va]

Hi KT!

you need to activate it in "Advanced features -> Allow tri-state connections":

Once you do it, for example in code block appears two new input types:

These are the same (inout/tristate port), the only difference is in wich side of the visual block do you prefer to show (at the left side or at the right).

Cheers!

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[KT Chiam]

Hi Charli,

Thank you for your quick response! After enabling the 'Allow Tri-state connections', I can see additional option, although it is not same as your screen.

How can I set it as input at some time and output at other time? The pin wiring will cause invalid connection if I wire constant bit to an tristate output.

Thank you

Best Regards,

KT

[charli va]

Hi KT! yes, my screenshot is from "code block config" in ports like in your snapshot you need to activate  "inout" pin.

Yo need to select the port in the bluebox (now is in null and icestudio not know what port are you binding) .

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[KT Chiam]

Hi Chatty,

I try to enable "inout pin", but there is still 1 port on the block, depending on I select Input or Output port initially. I saw an example by Obijuan. Is this the way to do it?

Thank you.

[charli va]

Hi KT i don't understand you well, but i'll try to explain me.

The "inout" pin only need "one pin" to do the "in" or "out" function.

In your verilog code block you could use the pin that you define as inout as tristate pin. At that moment, if you write values in this pin, the pin acts as "out" but, if you want to read from it "in" you needs to put this pin in Z state.

You could view a verilog example here https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/ver-bidirec.html

The other snapshot , the green block,  is other way to do an inout pin based in fpga primitives. Obijuan has an awesome documentation about it using this kind of blocks , https://github.com/Obijuan/Cuadernos-tecnicos-FPGAs-libres/wiki/CT.3:-Pines-de-Entrada-Salida, is in Spanish but i think you could translate with some automatic tool.

i hope this help you.

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