Añadida placa 5A-75E al IceStudio/Apio y funciona perfectamente

[beni...@gmail.com]

Buenas a todos

Acabo de completar con exito la inclusion de las placas ColorLight con la FPGA ECP5 al icestudio en windows

La placa que tengo es una ColorLight 5A-75E

Utilizo como programador un FT2232H.

Si quereis usar otro programador podreis usar los compatibles para la aplicacion OpenFPGALoader  pero hay que realizar un pequeño cambio en el Apio que os puedo decir. De todos modos no veo la necesidad de usar otro programador ya que los demas tardan mas.
Unos parrafos mas abajo os comento como configurar el FT2232H en Windoiws para usarlo con vuestro Icestudio/Apio

He añadido las siguientes placas con sus pines y programandolas con un FT2232H externo

- ColorLight-5A-75B-V61
- ColorLight-5A-75B-V7
- ColorLight-5A-75B-V8
- ColorLight-5A-75E-V6

- ColorLight-5A-75E-V71

- ColorLight-i5-v7.0   (esta ultima habria que programarla con el FT2232H externo)

Ahora me preguntareis por que no hago un pull request?  
Puedo hacerlo para el icestudio sin problemas, pero para el Apio aparte de los archivos de configuracion, hay que añadir el paquete de opeFPGALoader y yo he añadido eso a mano en windows, no se como lo hace el instalador de Apio y eso lo tendrian que hacer sus creadores. (ver punto 1 de como modificar Apio mas adelante)

Os paso los archivos por si quereis insertarlo a mano en windows

Todos los archivos los teneis aqui en Mega
https://mega.nz/file/9x8QTIjJ#dryn_qztE1Zc17RWFqCNEwBs7TX63Pz3ujq_my_HzKQ

Icestudio 

1) En la carpeta -> C:\Program Files\icestudio\resources\boards
Añadir el contenido del ZIP Icestudio_add.zip     (sobreescribir el archivo menu.json)

APIO
1) En la carpeta -> C:\Users\tu_usuario\.icestudio\apio\packages
Agregar el contenido del zip toolchain-opefpgaload.zip
2) En la carpeta  --> C:\Users\ tu_usuario\.icestudio\apio
Sobreescribe el archivo profile.json contenido en el archivo profile.zip
3) En --> C:\Users\tu_usuario\.icestudio\venv\Lib\site-packages\apio\resources

Sobreescribe los archivos programmers.json y boards.json  contenidos en el archivo resources.zip 

4) En --> C:\Users\tu_usuario\.icestudio\venv\Lib\site-packages
Sobreescribe el archivo util.py contenido en el archivo util.zip

Para Linux

Entiendo que salvo el toolchain-openfpgaload.zip que contiene el ejecutable para windows, si lo sustituis por el ejecutable para linux, deberia de funcionar todo en linux tambien

En linux tendreis que añadir el FT2232H a vuestras udev/rules
y descargaros el ejecutable para linux desde 
https://github.com/trabucayre/openFPGALoader

y meter el ejecutable openfpgaloader (ojo que hay que ponerlo en minusculas) de linux  en la carpeta C:\Users\tu_usuario\.icestudio\apio\packages\toolchain-openfpgaloader\bin

Programador FT2232H y como usarlo en Windows para ICeStudio/Apio

Como yo uso el programador FT2232H como programador Xilinx, para evitar dejarlo fijo con el driver Libusb  y poder usarlo con el ISE o el VIVADO hay que usar el USB Drive Tool

Descarga la utilidad USBTool desde https://visualgdb.com/UsbDriverTool/

El archivo a descargar es este: http://sysprogs.com/getfile/413/UsbDriverTool-2.0.exe

Instalalo y ejecutalo el UsbDriver

 USB Seria Controler A es nuestro JTAG FT2232H  , y como se ve inicialmete sin nada entre parentesis funcionaria para Xilinx

Para que funcione para Latice con el ICeStudio has de hacer lo siguiente

boton derecho encima del "USB Serial Controler A"  y seleccionas Install Libusb-WinUSB

Ahora a la derecha del nombre veras entre parentesis (Libusb - WinUSB)

Ya puedes trabajar con el en icestudio sin problema 

Para volver a dejarlo como estaba inicialmente y que funcione en Xilinx de nuevo has de hacer de nuevo boton derecho y seleccionar Restore default driver  ya volvera al principio como estaba (sin nada entre parentesis), pudiendose utilizar en Xilinx sin problema

No dudeis en consultarme si teneis algun problema

Un Saludo y disfrutad de las nuevas placas

Fernando Mosquera

[beni...@gmail.com]

Se me ha olvidado algo muy importante , debeis de partir de la version ultima WIP del IceStudio para añadir los cambios
Bajada de aqui
https://downloads.icestudio.io/
Yo uso la version  0.5.1w210224

Saludos

[Steinþór Hafsteinsson]

Hello Benito.

This is amazing work and I'm looking forward to testing this. Thank you very much for taking the time and effort to make this work available to us all. I hope we will see this integrated into both Apio and Icestudio soon.

I'm not sure if I have an FT2232H adapter. The i5 variant uses an STM32F103 MCU to interface with the i5 module. It is configured as an ARM Daplink, (https://armmbed.github.io/DAPLink/), which shows up as a small flash drive when you plug it in. There is a tool called ECPdap that can be used to flash the image from the cli. Here's the github if anyone is interested https://github.com/adamgreig/ecpdap. I have used that to flash the board and it works fine.

I just want to thank you sincerely for your effort.

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

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[beni...@gmail.com]

Hello Steinthor

I can include your board in IceStudio but first we are gonna to be sure that it is the same board

Now I have included this board --> Colorlight i5-v7.0  from here --> https://github.com/wuxx/Colorlight-FPGA-Projects

There is another board --> iCESugar-pro from here --> https://github.com/wuxx/icesugar-pro
Please, could you confirm which is your board??

You said that you flash your board with ECPdap from cli
1) What is the command you are using ??   is this your command line  (ecpdap program Your_bitstream.bit) ??? 

2) Are you running in Linux or a Windows OS ?
     If you are running in Linux, do you need to include the USB device detected in the OS in the  udev rules ??

Thanks and regards

Fernando Mosquera

[Steinþór Hafsteinsson]

Hello Benito

Now I have included this board --> Colorlight i5-v7.0  from here --> https://github.com/wuxx/Colorlight-FPGA-Projects
There is another board --> iCESugar-pro from here --> https://github.com/wuxx/icesugar-pro

Please, could you confirm which is your board??

I have the  Colorlight i5-v7.0

You said that you flash your board with ECPdap from cli
1) What is the command you are using ??   is this your command line  (ecpdap program Your_bitstream.bit) ??? 
2) Are you running in Linux or a Windows OS ?

     If you are running in Linux, do you need to include the USB device detected in the OS in the  udev rules ??

1.) I use ecpdap flash write bitstream.bit https://github.com/adamgreig/ecpdap

2) I run both Windows and Linux, depending on my mood, and mostly to be able to run some MCU toolchains that are hard to get to work properly in Windows. My preferred distro is Manjaro. I did not have to add any udev rules, just needed to make sure I had acces to the USB and serial connections by adding my user to the UUCP group, I don't remember atm what group that is on Ubuntu or Debian based distros. I followed this guide to get started: https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html there is also some info for Colorlight boards at https://github.com/kazkojima/colorlight-i5-tips

Thank you very much for looking into this for me. 

____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/406293f7-9ad8-41ce-9d5c-6c2332d5f449n%40googlegroups.com.

[beni...@gmail.com]

Hello Steinthr

I gonna add the Colorlight i5-v7.0 with support of ecpdap but the command line to use to flash the FPGA board will be  "ecpdap program --freq 5000 blink.bit"  .  
ecpdap flash write bitstream.bit  is for save the bit in  spi flash , and when you use Icestudio you don't need to save in SPI Flash.

Tomorrow I will give you more news

Thanks and regards

Fernando Msquera

[beni...@gmail.com]

Hello Steinthr

I have already added the Colorlight i5-v7.0 board with support of the ecpdap programmer  in IceStudio and Apio 

Follow the next changes to add all Colorlight boards from the 0.5.1w210224 version downloaded from https://downloads.icestudio.io/  

The required files are included here -->  https://mega.nz/file/dk9mUIob#o71vPHwmAWaNyYgpZMf7sVvkil6CZeblcKeHxyh3_Js

Icestudio 

1) In the folder -> C:\Program Files\icestudio\resources\boards
Add the files of  Icestudio_add.zip     (overwrite the menu.json file)

APIO
1)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages
Add the files of    toolchain-opefpgaload.zip

2)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages
Add the files of    toolchain-ecpdap.zip
3)  In the folder    --> C:\Users\ your_user  \.icestudio\apio
Overwrite tIn the folder he In the folder   profile.json file of profile.zip file

4)   In the folder   --> C:\Users\your_user\.icestudio\venv\Lib\site-packages\apio\resources

Overwrite programmers.json y boards.json  files of  resources.zip  file

5)  In the folder  --> C:\Users\ your_user\.icestudio\venv\Lib\site-packages
Overwrite util.py file of util.zip file

The speed of the programming your board will spend the same time that when you use the  "ecpdap program --freq 5000 blink.bit" command in the CLI. How long is it?

If it is slow , maybe is better to use a external FT2232H programer. Please keep me updated

Thanks and regards

Fernando Mosquera

[charli va]

Hola Benito!! muchísimas gracias por esta aportación!! voy a ver como va el tema de apio que yo en eso no estoy muy al día y te indico como hacer los pull requests para que subas tus aportaciones.

Te digo algo pronto, voy a ponerme al día con ese tema.

Una vez más muchas gracias!

--

[beni...@gmail.com]

Hola charliva

El problema del pull request en el Apio es que en el instalador se leen y se descomprimen unos paquetes que se supone son los toolchains de los ejecutables de los ficheros que se usan para programar
En nuestro caso son el OpenFPGALoader y el ECPDAP y esos ficheros creo que tienen unos requisitos especiales
Ademas esos paquetes deberian de estar hechos tanto para la version Windows como para la version Linux.
Yo todas las pruebas que he hecho han sido en Windows, supongo que en linux sera igual, solo cambian los ejecutables de los toolchains a linux (punto 1 y 2 del APIO de las instruciones ultimas que postee antes en ingles)

Un saludo

Fernando Mosquera

[charli va]

Si si, leí tu mail, efectivamente hay ue crear las toolchains, es lo que voy a mirar para que puedas hacer el resto de pull requests ya con la toolchain nueva preparada dentro de apio y así que todo pueda funcionar perfectamente.

En cuanto lo tenga te aviso.

Gracias!

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/6db3af3f-8906-48d3-9f92-f63af2b04bb7n%40googlegroups.com.

[Steinþór Hafsteinsson]

Good morning Benito

I am very, very grateful to you for taking the time to create the support for this board for me. In fact I find it hard to find the right words to describe it. 

I really hope that this can be formally included into both APIO and Icestudio. You have done incredible work to achieve this, maybe others will now consider this board, it is a very cheap ECP5 board with a whole lot of pins and great potential.

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/CAEQ-VCZiOh78JA%2BfzOT_R6ka9Q5GjdbeAnhN1_U0T5juUwunhg%40mail.gmail.com.

[beni...@gmail.com]

Added the two versions of Colorlight-i5 depending of the used JTAG programmer. 

I will upload the changes later

Regards

Fernando

[beni...@gmail.com]

Today, I was working with the Colorlight 5A-75E board to try to use other programmer. It is possible to use the next programmers

1) FT2232H (and digilent variations based in FT2232H -> STM1 for example)    I recommend this --> https://www.aliexpress.com/item/32806818411.html

2) FT232H (and digilent variations based in FT232 --> digilent hs2 or hs3)          I recommend this --> https://www.aliexpress.com/item/33052982174.html

3) USB Blaster    I recommend this --> https://www.aliexpress.com/item/32825776038.html

FT22232H is showed in the next picture

And USB-Blaster is showed in the next picture

Both programmers are working with IceStudio/Apio but while FT2232H spends less than a second to program the board, USB blaster spends 4-5 seconds.

I don't have a FT232H but I suppose is gonna be fast too, close to the FT2232H.

If somebody is gonna use any of this new programmers please, contact with me and I can add easily to IceStudio/Apio form Colorlight 5A-75B or 5A-75E boards.

I have already added the USB-Blaster programmer for my ColorLight 5A-75E but I can add it in any ColorLight 5A-75* version board.

Likewise, I have taken off the Level shifters form my board

Now I am waiting for the small Bypasses that I have ordered here -->  https://oshpark.com/shared_projects/Og8YtGBU

The idea is solder them is this way

When I have done the substitution of the level shifters by the bypasses , the board will have 96 pins I/O at 3.3 V as a regular Lattice board

Regards

Fernando Mosquera

[Steinþór Hafsteinsson]

Hello Benito.

It's interesting how fast you are able to flash the board. The STM32 Daplink is slow. I'm getting about 30-40KB/s for a 1MB file that takes close to a minute to flash. I donðt know how closely you studied the i5+carrier combo that I sent you links for. The carrier board connects to the module's JTAG with 4 pogo pins. If those are proper JTAG pins and I'd be able to connect to them, do you think I could use a J-link or ST-link to program the board? I know you don't have a board to test and verify it, I'm just asking for the best guess given the information you have. I do have some USB to serial connectors, one of them supports RS484, if I ask you to guess again might that be useful?

Is the photo above your soldering work? If it is, that's some mad skillz you have.there. I don't have the best record when it comes to fine soldering work. I look forward to hearing about your progress on getting the board functional.

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/c4c7b777-128f-4573-b6e8-3d7c8579ec84n%40googlegroups.com.

[beni...@gmail.com]

Hello Steinthor

If Dpalink with ECPDAP is slow, it is better to use the JTAG inputs of the board and use and external programmer. The connections of JTAG are showed in the red line

JTAG is a connection that use 6 pins, TCK, TMS, TDI, TDO,  and you need 2 more,  3,3 V and GND (This two are common in the board)

For example you can use 3.3 V and GND of the P6

You can use any JTAG programmer that I have recommended in my last message, FT2232H or FT232 (or variations) are mainly recommended 
You need a fast JTAG programmer , J-link or ST-link  are not a JTAG programmers 

There is a USB to serial connectors that is supported by OpenFPGALoader as a JTAG programmer, the FT232RL is a  generic USB<->UART that converters in bitbang mode, so it is too slow.
I said before the best JTAG programmers for your ECP5 board are FT2232H, FT232H or USB-Blaster.

In the last version of my IceStudio I have added the different options of JTAG programmers for the boards

Regards

Fernando Mosquera

[Steinþór Hafsteinsson]

Hi Benito you are awesome when it comes to getting these boards to work. Thank you for your excellent, selfless contributions.

Can you tell me what is your JTAG programmer? Or give me a link to a similar device?

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/90c84515-f77a-4a0f-a082-b12ab4c6f05bn%40googlegroups.com.

[beni...@gmail.com]

Hello Steinthor

My JTAG programmer is the FT2232H   from here --> https://www.aliexpress.com/item/32806818411.html

Because I use the same programmer in other Xilinx Boards I have applied a mod to this programmer (If you only are going to use for Lattice  ECP5 board you don't need to do it)
The mod is based in change the content of its EPROM , here you have the instructions  -->  https://gist.github.com/rikka0w0/24b58b54473227502fa0334bbe75c3c1

In the same way of other boards in IceStudio, you can use Zadig to install the LibUsbK driver if you want to use the programmer in IceStudio/Apio.

If you applied the mod of the EPROM  and you install the Xilinx Drivers, in Zadig you will be the FT2232H board as Digilent Adept USB Device (Interface 0) and you can install the driver libUsbK



But in my case, because I use the board for Lattice ECP5 and for Xilinx boards in ISE/Vivado, I don't use Zadig to install the LibUsbK driver because the FT2232H programmer will not work with Xilinx IDE. So, to easily recover the original driver that works in Xilinx , I use an alternative method.  First, I install the Xilinx driver of the FT2232H board after modifying the EPROM and later I use the alternative method to modify the driver.

How to install and change the LibUSbK driver (Alternative Method to Zadig. It allows recover the driver easily) 

I use the utility  USB Driver Tool,  you can download from https://visualgdb.com/UsbDriverTool/  , The last version is here --> https://sysprogs.com/getfile/1372/UsbDriverTool-2.1.exe

In case you use the FT2232H JTAG programmer, you will see the "USB Serial Converter A" with VID 0403 and VPI 6010

So, You have to press right mouse button over it and select " Install Libusb-WinUSB"



You will see in the line of "USB Srial Converter A"  in parenthesis Libusb-WinUSB.  In this moment you have the drivers already installed



If you want to revert the original driver of the FT2232H in order to use with Xilinx ISE or Vivado IDE , you only has to press right button over "USB Serial Converter A" again and select "Restore default driver", the driver will be restored to the original.

And you will see the original state with the device name without nothing in parenthesis . Now the board has recovered the original Xilinx sriver and I can use it in ISE and Vivado Xilinx IDEs 

In this way you can use the FT2232H JTAG programmer with any board  
The way to install the driver is equivalent for FT232H or USB-Blaster programmers

I hope this explanation helps you 

Regards

Fernando Mosquera 

[beni...@gmail.com]

I forgot to put the connections of the FT2232H boar to connect to the board. Here you have it  (Sometimes it is not necessary connect the VCC connector)

If you apply the MOD of the EPROM, you will have an USB-UART converter in the Second port "USB Serial Converter B" and you can use as a traditional USB-UART convertor

Regards

Fernando Mosquera

[beni...@gmail.com]

Last Boards Update 2021-02-31

Regarding of the JTAG programmer, added new versions for

• ColorLight-5A-75E-V71_(FT2232H)
• ColorLight-5A-75E-V71_(FT232H)
• ColorLight-5A-75E-V71_(USB-Blaster)
• ColorLight-i5-v7.0_(FT2232H)
• ColorLight-i5-v7.0_(FT232H)

Follow the next changes to add all Colorlight boards from the 0.5.1w210224 version downloaded from https://downloads.icestudio.io/  

The required files are included in Icestudio_update_boards_20210331.7z   here-->  https://mega.nz/file/4plAFT5C#MML-Yj1-6FQbVHAUc3iRGGqvEW2Dib-L2BT-Xhkv0rQ

Icestudio 

1) In the folder -> C:\Program Files\icestudio\resources\boards

Add the files of  Icestudio_add.zip     (overwrite the menu.json file)

APIO

1)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages

Add the files of toolchain-opefpgaload.zip

2)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages

Add the files of toolchain-ecpdap.zip

3)  In the folder    --> C:\Users\your_user\.icestudio\apio

Overwrite profile.json file of profile.zip file

4)   In the folder   --> C:\Users\your_user\.icestudio\venv\Lib\site-packages\apio\resources

Overwrite programmers.json y boards.json  files of  resources.zip  file

5)  In the folder  --> C:\Users\your_user\.icestudio\venv\Lib\site-packages

Overwrite util.py file of util.zip file

Regards

Fernando Mosquera

[beni...@gmail.com]

Hello Friends

I have already put all my Bypasses in my Colorlight E5-75E board

I just test the IceStudio software with this example

The board has 16 HUBS named from J1 to J16

And the available pins for each HUB are 6 --> R0,  R1, G0, G1, B0, and B1

The position of the HUB is showed above

Here you can see the example using an external pin in J1

Regards

Fernando Mosquera

[beni...@gmail.com]

He subido un video donde podeis ver como se programa la placa ColorLight 5A-75E con el ICeStudio y como, despues de poner los Bypasses, funciona un pin externo sin problemas 

https://vimeo.com/533802114

Espero lo disfruteis 

Saludos

[Manuel Pascual]

gran trabajo fernando! un placer ver tus progresos. felicidades y suerte!

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[Obijuan]

Hola Fernando!

Muchísimas gracias por todo tu trabajo. Este cuatrimestre estoy casi sin tiempo, pero en cuanto pueda te echo una mano en la integración de las toolchains en apio/icestudio

Saludos, Obijuan

[charli va]

Hola Benito! enhorabuena por los avances!! la verdad que estás haciendo un trabajo estupendo y esta tarjeta abre muchas posibilidades.

A ver si en las proximas semanas vamos sacando tiempo para dejarlo actualizado en icestudio.

Saludos!

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[Steinþór Hafsteinsson]

Hello Benito or should it be Fernando, I've been addressing you according to your e-mail address, please advise if you have a preference for which.

You have been working very hard on getting your board active and I have to say I'm impressed that you have managed to do all that soldering, I'm not that handy with a soldering iron.

And you have been actively working on implementing it in Apio and Icestudio. I have not been able to put much time into testing those modifications for my Colorlight i5, but I will update the thread when I have any new information, I am also waiting on a similar FTDI controller as the one you have. I'm also very tempted to act like the fool that I am and order a Icesugarpro, not that I have need for it pure hardware addiction and techno hoarding 😜🤓

Hello Carlos I really hope you can find a way to enhance Icestudio with the addition of these cheap but potentially powerful boards.

I want to check since some boards allow you to map out very many pins, and there are boards like the Icesugar and the EDU-CIII?? FPGA that have PMOD connectors for quick IO development. Is there some way to streamline pin assignments in Icestudio so that you don't just have one deep menu for assigning outputs. The way it is now works, but as you step into larger FPGA's like the ECP5 boards with more pins selecting them becomes awkward and tedious. I have a vague idea for a way, whether it's good or bad I dunno. 

If Icestudio could add "virtual" io blocks based on the selected board. Those io blocks would only be a UI element, all pin mappings would function as they do now. But the blocks you would be offered would be based on what the selected board offers, so for alhambra II for example if you created a LED output block you would only have to select the proper LED pin, but not go through a list of every pin on the board. 

Or some multi list selector, where you would see a list that allows selecting sublist depending on board specific layout like LED's or PMOD1 after you select one of those another list shows up where you can select which specific LED you want to map. I have seen lists like those used on many support sites where I find for instance my motherboard drivers. I can scroll straight to my board or select by CPU manufacturer -> chipset -> motherboard line -> specific mother board, and so on.

I'm having problems describing things properly I hope you can get some sense out of this

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/CAEQ-VCYMJFwB%2BARko%2BEArOB08wDbdyV4PmW%3DKhac4tWLYh%3D7Cg%40mail.gmail.com.

[Jo mo]

Hello Francisco,

Can you please crosscheck if there is a little typo error for a directory in your instructions.
At the step 5) (or 4) in Spanish)

“

5)  In the folder  --> C:\Users\your_user\.icestudio\venv\Lib\site-packages
Overwrite util.py file of util.zip file
"

It seems to me that in the original icestudio installation, util.py is in the folder C:\Users\your_user\.icestudio\venv\Lib\site-packages\apio

But even with this modification, icestudio can still not communicate with my colorlight i5.
It seem I have a problem with ecpdap on my win10. Which is weird because ecpdap is fully working on a linux VM on the same machine.
It will be nice if you can make some precise (for linux noobs) instruction for the icestudio modification on a linux system.

Anyway, thanks for that good work.
Have a good Sunday

Joaquim

[beni...@gmail.com]

Yes Joaquim 

Your are right , there is a typo in mi instructions. below you have the right instructions.

Remember that the instructions are for windows, for Linux I suppose the procedure is similar.

---------- -----------------------------------------------------

Follow the next changes to add all Colorlight boards from the 0.5.1w210224 version downloaded from https://downloads.icestudio.io/  

The required files are included in Icestudio_update_boards_20210331.7z   here-->  https://mega.nz/file/4plAFT5C#MML-Yj1-6FQbVHAUc3iRGGqvEW2Dib-L2BT-Xhkv0rQ

Icestudio 

1) In the folder -> C:\Program Files\icestudio\resources\boards

Add the files of  Icestudio_add.zip     (overwrite the menu.json file)

APIO

1)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages

Add the files of toolchain-opefpgaload.zip

2)  In the folder   -> C:\Users\your_user\.icestudio\apio\packages

Add the files of toolchain-ecpdap.zip

3)  In the folder    --> C:\Users\your_user\.icestudio\apio

Overwrite profile.json file of profile.zip file

4)   In the folder   --> C:\Users\your_user\.icestudio\venv\Lib\site-packages\apio\resources

Overwrite programmers.json y boards.json  files of  resources.zip  file

5)  In the folder  --> C:\Users\your_user\.icestudio\venv\Lib\site-packages\apio

Overwrite util.py file of util.zip fil

-----------------------------------------------------------------------------------------------

I don't have the Colorlight i5 board and I cannot test it, but I think the ecpdap system is a litle bit slow. First, you should try testing it  with the command line "ecpdap  program --freq 5000 blink.bit"  (use the blink.bit as an example to test it)

Anyway you can use the JTAG pins of your board and use another programmer (FT2232H or FT232H). I am sure it will work.

If you want to use the USB Blaster I can develop another version with it.

Regards

Fernando

[Jo mo]

Hello Fernando,

 Yes, you are right ecpdap is quite slow(it can take one minute to load a bit file). But as a STM chip is what is actually installed on the dev board!

 

Also, with this devboard and colorlight i5 board combo, we have to be careful to avoid connecting the jtag outputs of the STM chip and the jtag outputs of another programmer.

When the i5 board is well inserted in the sodim connector the 4 jtag pins are mechanically connected at the same time with the help of 4 spring pins (which connects the i5 board to the STM chip on the dev board).

So if we want to inject another jtag signal on the 4 pins of the i5 board, it may be necessary/safer to add an insulating plate between the spring pins and the i5 board for fully disconnecting the STM chip outputs.

see the following picture it may help understanding.

 In the future, I planned make my own pcb for connecting the i5 board(with a sodim +4 “spring” pins). And i will add on the pcb a connector for connecting a USBblaster. So yes, if you can implement the USBblaster it will be nice.

 

Concerning ecpdap on win10 or win seven (in two different machines).

It is able to see the programmer but not the jtag device.

On a windows terminal I got:

C:\ecpdap>ecpdap probes
Found 1 CMSIS-DAP probe:
  0d28:0204:070000010669ff343832434257103334a5a5a5a597969908 DAPLink CMSIS-DAP

C:\ecpdap>ecpdap scan
Error: specified probe not found.

 

And on the same win 10 machine but running a linux VM, it works fine :

q@q-virtualbox:~$ ecpdap probes

Found 1 CMSIS-DAP probe:

  0d28:0204:070000010669ff343832434257103334a5a5a5a597969908 DAPLink CMSIS-DAP

q@q-virtualbox:~$ ecpdap scan

Detected JTAG chain, closest to TDO first:

 - 0: 0x41111043 ECP5 LFE5U-25 [IR length: 8]

q@q-virtualbox:~$

And I can load bitstream with the terminal. But on this linux VM I didn't yet manage to configure well icestudio!

regards

joaquim

[Steinþór Hafsteinsson]

I have found the i5 to be very sensitive when it comes to achieving a solid connection to be able to flash it. Sometimes just moving it slightly is enough to make the connection to the board to fail. That is usually due to the jtag pins not getting a firm connection and putting your finger on that corner and applying a slight pressure on it usually solves the communication problem. 

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/8e31e294-8e9e-45fc-ad83-e22fe8f41df3n%40googlegroups.com.

[Jo mo]

Hello Steinor,

Therefore, did you manage to program your colorlight i5 board using the usb connector of the devboard:

  - With icestudio on windows 10 (using ecpdap)?

  - Just with ecpdap on a win 10 cmd terminal?

I only make it work using ecpdap on linux and it work very well (no need to push on the jtag pins for now :-).  but without icestudio for now.

Regards

Joaquim

[beni...@gmail.com]

Maybe the problem of ECPDAP in windows is relative to the driver LIBUSBK, maybe you have to use ZADIG or the solution I posted before to avoid problems in windows  (look at my message of Mar 31, 2021, 12:02:55 PM)
May programmers as FT2232H, FT232H and USB Blaster require that you force the LibUSBK drive installation.

I will add the USB-Blaster programmer to ColorLight i5. Later I will post the update version with the changes

Regards

[Jo mo]

Yes I tried about everything with ZADIG and the usbdrivertool.

Mainly, installed winusb(libusb) driver for the CMSIS-dap daplink(see picture) but no improvement.

Yes, understood that libusbk is for the FTDI chips and not the stm32 ones.

I just ordered a usbBlaster (it will be there in one month :-) )

Thanks a lot for your replies

Joaquim

[beni...@gmail.com]

Added the Colorlight i5 (USB-Blaster)  in the list of boards

You can download the last version in my  Github here:

https://github.com/benitoss/ColorLight_FPGA_boards/blob/main/README.md

Regards

[Jo mo]

Muchas gracias Fernando,

I have just to wait 3 weeks for the delivery of my alliexpress usbBlaster.

In the meantime, I will modify slightly my colourliht i5 devboard to allow it to be programmed by this programmer. I will post a picture here.

Have a good day.

Joaquim

[Jo mo]

Here are few pictures of my colorlight i5 modification (for USBblaster compatibility).

 

Good news, i found an FT2232H mini module in one of my drawers. So no need to wait for the delivery of my aliexpress usbblaster to test icestudio with my colourlight i5 board.

Anyway, the update of colorlight i5 (usbblaster) will also be useful because it offers a cheaper solution for the masses ;-)

 

A little remark Francisco :

In your message of 31 march at around 9h33m49s(+/- few hours depending on your time zone)J

You recommended connecting the 3.3 V on the i5 dev board side.

But when the dev board is powered with its main power source, (like you are also doing with your colourligth 5a-75E board), and another 3.3V is connected in the same time from the programmer side, we may have a short-circuit conflict between two different 3.3V regulator outputs.

This may induce a current from the higher voltage regulator (eg 3.35V) into the lower voltage regulator (eg 3.25V). And as the connection resistance is very low, we can have an unwanted high current consumption and (even a component damage potentially).

Thanks again for all that good stuff Francisco

Regards

[Jo mo]

Oups,

Sorry Franscico, i just understood thaht the last part of my previous message was wrong.

The programmers need, in fact, to read on their VCC (TRGT) input the 3.3V of the target device.

So for the "Diy" programmers like FT2232h, ft232H, we have just to be carefull to connect this line to a VCC(trgt) pin and not a VCC pin.

[beni...@gmail.com]

Hello Joaquim

First , my name is Fernando, not Francisco ,but If you prefer call me Francisco is OK  8-)

Fantastic News !!! You can use the FT2232H programmer that is faster.

Finally If the board is power on, you do not need to connect the 3.3 volt into the FPGA board, with only 5 pines is enough  (4 for JTAG + GND)

I hope you can program the board perfectly

Please, Keep me updated with your progress

Thanks and regards

Fernando Mosquera

[Jo mo]

Sorry Fernando,

But you now i have an uncle called Fransisco :-))

So i could program my first design with icestudio.

- injected a square wave in an input and it went out correcly at the expected output.

- i have seen a very small issue.

The colourligtht i5 onboard led is inverted probably mounted active low. No probs i can live with that. :-)

 These icestudio stuff with all his collection libraries look very very interesting specially for Verilog and FPGAs beginners like me...

Have a good day.

[beni...@gmail.com]

Hello Joaquim

In my Colorlight the onboard green LED is mounted active low too

The way to test it is using this simple construction

If the LED is turning on means that is Active low and the schema is like you posted before

Regards

Fernando

[Jo mo]

Yes Fernando, I did exactly that and got the same result as you .

it is just that a zero which turns on a led is a bit counter-intuitive :-)

But anyway,  as this led is mainly used for our test during the devellopment of our code, we just have to get used to it ;-)

Regards

joaquim

[Jo mo]

Hello Everybody,

I don’t know if it is related to the colorlight i5 toolchain or to Icetudio but I have strange think here.

With the above simple 4 bits counter circuit, if:

-          I make an verify/build/upload

-          And I just make changes in the ouput numbers. (eg  P2_L18  becomes P2_L20)

-          I make second verify/build/upload

Then my logic analyser does not see any wiring change on the ouputs signal.

So it seems thaht the second upload was identical to the first one!

To make it work as expected I had to add a step in the sequence:

-          I make an verify/build/upload

-          I make changes in the output numbers. (eg  P2_L18  becomes P2_L20)

-          I add block (eg: constant block left unconnected on the workspace)

-          I make second verify/build/upload

Then, my logic analyser see all the wiring changes on the output signals.

Any ideas?  i joined the .ice file

Have a good evening

Joaquim

[beni...@gmail.com]

Hello Joaquim 

The problem  I have detected with the ColorLight board is that if you only change the pins in one project, the changes don't update the BIT file.

 You need to change anything in the project (add a new block or change something in the structure of the project), the only assignation or change of pins does not change the BIT file and you will program the board with the first BIT file before the pin changes.

If the IceStudio WIP version is working perfectly with any ICE40, I suspect this problem is related to the ECP5 toolchain. 

Maybe one person that is using any ULX3s board can solve our doubt. But, I afraid that the problem will be reproduced in any ECP5 board 

Regards

Fernando Mosquera

[Juan Gonzalez Gomez]

Yes, it is a bug in Icestudio that affect the  ECP boards (not ice40)

It would be great if you could file an issue giving all this information

Thanks

Best regards, Obijuan

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/5662c9ab-39c0-42af-bbe7-75d1fe879e29n%40googlegroups.com.

[Jo mo]

Ok obijuan,

i will,today, try  to summarize these 3 last messages adding an issue on github / icestudio

Thanks you both.

joaquim

[beni...@gmail.com]

I have a project that is incompatible with icestudio and ECP5.
The project is the implementation of a SNES controller 

With my Colorlight 5A-75F, the instance is only working with the r botton if I don't connect the rest of output LED blocks.

 When I connect more than r , there are not signals of CLK_SNES and LATCH, so the physical SNES controller doesn't receive these 2 signals and doesn't send the LATCH signal to the FPGA.

Maybe is a problem of a CASE statement in IceStudio, it is really strange 

With this construction I can get the LED-r ON when I press the r button.

I got the instance from here :https://fpgalover.com/ip-cores/snes-controller-core
You can connect the Vcc of the controller to 3.3 volt 

The connections are 

Please, could anybody that use Alhambra test this project using your onboard 8 LEDs to test at least 8 actions of the controller ???? 

Thanks and regards

[Steinþór Hafsteinsson]

Hello guys

I've been trying to get the Colorlight i5 to work in windows and there are some problems getting it to flash and I don't know how to get that to work, and í don't know where the full error log goes. So I thought I could try using Icestudio in a clean linux installation and replace the appropriate files there. The first problem I found is that I don't know how the appimage integrates into my installation ad where the files go, so that I can add the board entries to Icestudio.

From what I can see I don't think that the files to be replaced are OS specific, although their locations may be different between oses. I'm running Manjaro but I also have Mint and Deepin installed, noth are Ubuntu based and installing Ubuntu or Debian depending on what distro is used to build the appimages.

So Carlos I would really be interested in knowing what the Icestudio appimage does when it integrates into my installation and particularly how to change the files for the board list. And of course how I can change the Apio files that are linked to the installation.

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/a2c0366a-4dd1-4a4e-a804-161c61e0e4b5n%40googlegroups.com.

[Jo mo]

Hello Fernando,

I am struggling with those icestudio savings problems.

I isolated a very simple case (see joined file) thaht may be eazy to debug.

On my machine, when:

-           I save the file (even with a new file name / “save as” ).

-          Quit / close the file

-          Then reopen it

I have 4 pins (out  of100) that are saved as other pins .

 

Before saving and quit                at reopening

P3_C1                      ------>                 P3_C17

P3_D2                      ------>                 P3_D20

P3_B1                      ------>                 P3_B19

P4_E1                      ------>                 P3_E19

 

Before opening an issue on the icestudio github page, I would like to tri to see that my icetudio installation is not corrupted.

So could you please check also on your machine by loading the file without converting it to a different board. I am using the ColorLight-i5-v7.0_(FT2232H).

 

As we actually do not need to have the dev board connected for making this test, I will try to see if I can reproduce this on the Alhambra board pins.

Other question, is there a reason for not inserting also the P1 connector (ETH ports) in your pinout.json file? Even if I do not need those for now J

 

Thanks

 

Joaquim

[Jo mo]

Interesting.

I just tried my .ice file (supplied in the last post) with the Alhambra II board selected and 2 ( out of 51) pin are also wrongly saved.

SDA   becomes ADC_SDA

SCL  becomes ADC_SCL

 

I think thaht I have a hint here.

All of this errors have something in commun. Text of the first is also fully present in the second one

P3_C1              -->                        P3_C17

P3_D2              -->                        P3_C17

P3_B1              -->                        P3_C17

P4_E1               -->                        P3_C17

 Alhambra II board

SDA   becomes ADC_SDA

SCL  becomes ADC_SCL

[Jo mo]

Hello Benito,

 I think we are all facing the same problems of saving/building/uploading. at least (see also https://github.com/FPGAwars/icestudio/issues/481)

it is probably different bugs that are messing  stuff an we have to try to isolate each of them.

Did you tried my. ice file in the previous files to see if you are getting the same error?

[Jo mo]

Ok, I just tried the obvious workaround:

Renaming in file “pinout.json” the problematic pins by adding an ”_”

 (eg:  P3_C1 changed to P3_C1_ )

And the problem is gone.

It seems evident that we have a weakness in the .Json files attributes reading.

So i will open an issue on icestudio/github because as the software is using plenty of .json files, the problem is maybe also happening with other attributes used in the software (causing potentially other issues).

[Jo mo]

Oups, Sorry

I just realised that I addressed my message to Benito instead of Steinhor in my message 3 hours ago! I should sleep more :-)

Steinor are you running your icestudio on windows with a "colorlight i5 ecpdap" selected board?

Personally, as I never managed to do that, neither  (like you) configure fully icestudio on linux .

I decided to mod my colorlight i5 board (see messages few days ago). And as Fernando (Benito) wrote, the programming of the chip is faster (~1 sec). This is quite nice for debugging sessions.

Joaquim

[beni...@gmail.com]

Joaquim,

I have opened your file test pin change saving.ice  and load in the Colorlight i5(FT2232H) as a board.
When I change the pin and save , the pin saved is ok. I don't see any error loading the file again. it keeps the last pin saved

The problem of icestudio is other, is when you change in one project of ECP5 the pins and upload the bitstream to the board. Icestudio don't change the last pin changes. to force to change the canges you have to modify other thing (or code or modify, create or delete any connection)

Regards

Fernando

[beni...@gmail.com]

Joaquin,

The real problem in ICestudio is that you cannot see the pins with a name larger than 5 characters, but it is only problem of that, the name of the pin is perfectly saved and working
I have just open an issue in icestudio github regarding with this problem  (https://github.com/FPGAwars/icestudio/issues/499)

Regards

Fernando Mosquera

[beni...@gmail.com]

Hello  Steinthor

ICestudio in windows works  , but if you cannot program your board probably you doesn't have install the LibkUSB driver. Thats is explained in my Github page -->  https://github.com/benitoss/ColorLight_FPGA_boards#jtag-programmers

Please read it carefully.  My suggestion is that you try to program the board in a command line first, if it works, Icestudio will work.

Anyway,  I gonna try to install the changes in an Linux version of ICestudio and maybe soon I will create a tutorial for it

Regards

Fernando Mosquera

[Jo mo]

Hello Fernando,

The problem was only with the 6 pins thaht i mentionned ( P3_C1 , ...).

But if you really tried with those -6 pins, it means that the problem was only on my machine.

With thaht type of problem and workaround i found. I was almost 100% shure thaht the issue was present in other computers! ??

[beni...@gmail.com]

Ok Joaquim,

I understand you, and your are right.
I think the problem is related to the saving the names of the pins in the IceStudio, only save 5 characters of the pins instead 6. And in that cases there are confusion between 

P3_C1 and P3_C17 , 

P3_D2 and P3_D20, 

P3_B1 and P3_B19,

P4E1 ands P4_E19

It happens between those shared pins because  ICestudio takes the last value of the list that share the same 5 first characters

Obijuan, another thing to fix in Icestudio, but it is realated to the same issue that I have posted before (https://github.com/FPGAwars/icestudio/issues/499)

Thanks and regards

Fernando

[Jo mo]

 Ok Fernando,

Looking at your board pinout.json file (ColorLight-5A-75E-V71_(FT2232H)).

I localised that we can expect a problem with the pin “CLK” which will be replaced by "Shared_CLK" .

I tried and, the problem is there.

So for now, if you want, you can apply the workaround i proposed earlier.

 

Regards

[beni...@gmail.com]

I am gonna change the pins Share_*  to be contained in 6 characters or less, I am gonna change to S_CLK o something like that

Thanks for let me know the problem

Regards 

[Jo mo]

i just tried what you wrote but it doesnt solve the problem because the string "CLK" is also include in "S_CLK".

so it is not a matter of numbers of letters at least for the saving problem.

Regards

Joaquim

[Jo mo]

So, or you rename the pin "Shared_CLK" to "Shared_CLoK" :-) 

or you have to rename the "CLK" pin

[Jo mo]

Hello,

For info, I received today my cheap UsbBlaster with a mysterious chip inside (IC ref laser erased)

And after loading the Winusb driver with zadig ,I tested it with my “slightly moded” colorligth i5 board and icestudio and everythink works fine so far on win10.

As Fernando have seen with his colorlight 5A-75 board the upload is slightly slower (13s) than with the FT2232 programmer (8s) for a same design.

Joaquim

[beni...@gmail.com]

Hello Joaquim

The USB-Blaster has several versions:

1) PIC18F14 without buffers (only 5V support)

2) STM32F101 (STM32F103 with USB Support)  and 74HC244 octal-buffer (2.0  to 6.0 V)

I was using in my tests the second one, and I think is slightly faster than the first one. It only spends 3 seconds more than the FT2232H programmer

Regards 

Fernando

[Jo mo]

Hello Fernando,

After reading your message, I was afraid of having partially damage my 3.3V fpga setup. Because my usb blaster looks like your first image, the one 5v powered.

Visually, my blaster has less components (no external quartz to clock the IC,…).

I measured the blaster and found that It has a 3.3V regulator. So only two ICs on this board ( the regulator  and the mysterious main IC).

So maybe a newer and cheaper to produce version of these blaster?! I got mine with the Alliexpress link you supplied us https://fr.aliexpress.com/item/32825776038.html

Great my board is still alive. :-) .

Well in a sense, i am waiting the moment where my 25KLut fpga fries;-)

if it happens, I will try replacing it with the 85KLut one ( with the same 381bga package ).

Remark: On the newer Icesugar-Pro board muselab used a smaller package the 281bga. So the max size upgrade is 45KLut (see ecp5 datasheet).

Why always more ressources?

The machine i want to devellop needs a maximun of ressources:

• i will use a small amount of those to drive the fixed peripherals(encoders/boutons/lcd screen)
• and the rest will be available to the user/maker for his custom functions and added peripherals.
  

It will be a big craisy fpga dev board. in a closed box. So a tool thaht the user can:

• shape to his needs (musical synth, autonomus fpga controlled lawn mower  :-), ... )
  
• and then use it in his every day life.

The most difficult part is the "shaping", and thaht is why it will be nice to have a "Userfriendly" fpga dev tool like Icestudio ;-)

Regards

Joaquim

[beni...@gmail.com]

Hello Joaquim, 

I don't know how is the USB-Blaster that you can get now from the Aliexpress. I have 2 different models but because I ask from different sellers. 

When you are goin to program your FPGA board usually you don't need to connect the 3.3 v line because the board is already power on.

So, the line 5 volt or 3.3. V of the USB-Blaster is doesn't matter

Anyway, it is very complicated to break your board.

I don't recommend you replace the FPGA with the 85K LUTs one,  probably IceStudio will be very slow with a project too big.
Remember that IceStudio was created initially for ICE40 with 4K - 8K LUTS.
So, I suppose that a project of 25 K LUTs will be really slow to work on it.

It will be better in that case work directly with an editor and Apio directly.

25L LUTS is enough size to create a develop board. There are other training boards with similar size.  Basys3 and Arty A7-35T have 35K, 

Regards 

Fernando

[Jo mo]

hello Fernando.

Well the 85 version has also 4 times more Bram, 7 times more dsp slices, ...
and theses dsp slices are quite promising for one of my hobbies (DiY musical instruments)
But ok, for now i keep calm and will take time playing with my 25 klut ecp5 ;-)

About the fpga ressources usage, you have probably noticed that they are not properly shown in icestudio bottom bar for our ECP5 boards.
To make it work, i modified two files :

C:\Program Files\icestudio/scripts/main.js

C:\Program Files\icestudio/views/design.html)

https://drive.internxt.com/5015f19b2f

Sorry but my html skills are poor, i was not able to place a good case/if statement in the html file,
So i commented some "ice40 lines", and replaced them by the suitable ones for ECP5  ( see <<ecp5>>  flags)

Maybe our icestudio devs can include a case statement somewhere to make it work for both fpga families without having to modify manually the files at every board change?
i will add a comment on the github open issue. https://github.com/FPGAwars/icestudio/issues/361.

Any way? if someone want to try this mod now, i strongly recommend to make a backup of your own version of these two files before overwriting them.

This is the result :

   

Remarks:

- I also added an indication of the build time.
this helps finding quicker that a launched build was not really performed.
on my machine, if the build time is  around 0.5sec, it means no new build done.
So i have to make a small design change like( adding a wire connection),(a port pin change is not sufficient);
And relaunch the build command.
Then the build is ok (build time is around 6 sec, depending on the designs).

So no need to open/refresh the " View/command output" window to check that the build was OK!

- looking at de data-sheets of my 25klut ECP5 fpga(page 23-24), i should have two DDRDLL in total but has you can see on the following picture it shows 4 units.

- and for the DLLDELD (just above) the quantities may be wrong  even for the 45/85 klut (not clear in the datasheet)!?

Is this a treillis question/problem?

regards

joaquim

[beni...@gmail.com]

Joaqim, 

The output now is working for ECP5 boards.

It is amazing !!!!

The part of DDRDLL is a value obtained from Trellis so it is probable the problems is coming form it.

Thanks for the effort 

Regards
Fernando

[charli va]

Hi Joaquim! if you want you could do a pull request with your enhances!

Thanks!

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[Jo mo]

Hi Carlos,

As it is now, this mod works only for one fpga family at a time. For instance ECP5
So the user has to edit the two files manually( switch the ecp5/Ice40 commented parts) to switch from  ECP5 to ICE40 board.
So is it a good idea to do a pull request in this case?

To make the file universal, we need to include a good if( or case) statement an this seems difficult in html. If nobody has easy solution to do it in the html, it has probably to be inserted in main.js.

with Maybe something like this(but it changes a bit more "the logics" of the code)

- in design.html:    
 
     <span> field1 </span>  
     <span> field2 </span>  
     <span> field3 </span>  
     .
     .
     <span> field10 </span>  
      
- in main.js:   
                  
  var ICE40 = ['Alhambra II', 'Icezum',......];     
  var ECP5 = ['colorligth_i5_ft2232', 'ULX3',......];
  selected_board = common.selectedBoard.name;
 
  if (ICE40.includes(selected board)){selected_board_family = "ICE40"}
  if (ECP5.includes(selected board)){selected_board_family = "ECP5"}
 
        switch (selected_board_family)
   case  "ICE40":
        return field1= "LC:"+xxx.used+" / "+xxx.total+ xxx.percentage +"+"%"
        return field2= "RAM:"+xxx.used+" / "+xxx.total+ xxx.percentage +"+"%"
        
        .
        .
        return field10= ""
        
   case  "ECP5"
        return field1= "LUT4:"+xxx.used+" / "+xxx.total+ xxx.percentage +"+"%"
        return field3= "SLICE:"+xxx.used+" / "+xxx.total+ xxx.percentage +"+"%"
        .
        .
        return field10= "Buidtime:"+xxx.value+" sec"

Thanks

joaquim

[charli va]

Hi Jo! this is not the best way to do generic, but i want to your user appear as contributor, the iniciative is yours.

Take me some time to think how is the best way to do it and tell you to implement and pull it.

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/7cc3cbb5-dccf-4cca-9b83-af2f139ccaban%40googlegroups.com.

[Jo mo]

Hi Carlos,

Don't worry i do not need to appear as contributor. All i want is a good opensource/ customisable software ;-)

So if you see that it is easy and it keeps the code less "patchwork looking", feel free to implement this yourself.

Take your time and let me know.

Thanks and have a nice day

[beni...@gmail.com]

The idea is thinking the best way to doing the changes for the future.
Now, the ice file saves the "board" filed , but maybe one of the important fiels to save in the ICE file is the  "type"  filed.
And the options of the field "type" are defined in the file menu.json

The new added option depends on the type of board:  HX1K, HX8K, LP8K, UP5K, and ECP5.  and other kind of boards that can be added in the future.

So, I am encouraging to the creators of ICeStudio to add that field in the ice file format, it will be easy to change the compilation visualization of each toolchain board family

Thanks and regards 

Fernando

[charli va]

Hi Benito! Thanks for the suggestions, they are welcome!

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/ba950d38-3d72-4c4a-b797-1b8f7fecbbe5n%40googlegroups.com.

[Steinþór Hafsteinsson]

Hello guys I've been absent from the forum here lately, due to the eruption volcano in my back garden. Well ok, my back garden isn't quite that biig but there is a cute little volcano some 20km as the crow flies from me. And as others I have been a bit obsessed about it. 

But I finally got a FTDI2232 programmer, I didnðt buy a identical version to yours Fernando I took this one, I like the box so the fragile electronics get damaged, since my organization method is nonexistent for the most part it might end up in some cox end get damaged.  Here's my version https://www.aliexpress.com/item/4001278638301.html?spm=a2g0s.9042311.0.0.6a7b4c4dyIOv6o.

I just wanted to ask if Fernandos modifications for the Colorlight boards to Icestudio ?

_____________________

Með bestu kveðju / Best regards

Here are links to webcams of the volcano, Note that the highest portion of the eruption column can reach about 400M. And the eruption activity is fairly stable, there are a few minutes where you only see the smoke and gasses. After that there is a period of turbulence in the lava lake and finally a strong eruptive column.  Best viewed between 22;00 to 03:00 since our night is getting consrantly shorter.

https://www.ruv.is/frett/2021/03/18/eldgosid-i-geldingadolum-i-beinni-utsendingu?utm_source=forsida_ruv&utm_medium=eldgos2021&utm_campaign=buttonLink

https://www.ruv.is/frett/2021/03/18/eldgosid-i-geldingadolum-i-beinni-utsendingu?utm_source=forsida_ruv&utm_medium=eldgos2021&utm_campaign=buttonLink

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/CAEQ-VCbyZopELR_1uqWz5O%2BC34UXVghXdJgVKtihvndpBY7u2w%40mail.gmail.com.

[Jo mo]

Hello Steinor,

i fear that you will have to go trough all this thread to have a good understanding of what you are doing. ;-).  For sure, all the info is there.

I remember that  Fernando as the colorlight 75A  board ( which as already the jtag pins on it available ).
And you have the same board as i have the colorlight i5. ( which do not have the jtag pins soldered, because it was initially thought to be programmed with the ecpdad/stm32 chip. )

So you have to solder the jtag pins yourself.

Personally as i was not really sure that the output of the stm32  will be tri-state/opened, i decided to add an electrical isolation (see one of my post few week ago).

So in the end i am programming the board with my ft2232 and powering it trough his usb3 connector .

good luck

Joaquim

[charli va]

I remembered you the other day when I saw news about the volcano, I am very glad that you are well and that you already want to continue doing things.

A hug!

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/CAGjhNWOV-0WM4UhCaX4nthDXnnsvm%2BrP-%2B0oNjxu44rP5yER7A%40mail.gmail.com.

[Steinþór Hafsteinsson]

Hello Carlos. From my simple mind adding the boards should be a relatively small patch. Fernando has done the heavy lifting by figuring out how to change the files that need to be changed, and has changed them so if you follow the instructions manually they work. It looks like it hardly needs to change the problem itserlf, just ass a python script that patches the files.. Then again I am a script kiddie when coding I mostly do cut and paste from google searches and do minor adjustments to the code so it more or less fits my needs.

_____________________

Með bestu kveðju / Best regards 

Steinþór G. Hafsteinsson / Steinthor ...

sgh...@gmail.com

Sími: 893-7656

Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/CAEQ-VCbahVGZ%3DqA0CQ%2BQKXUP_rtiCB8v0HZAAXW3519nN-hECg%40mail.gmail.com.