Digitizing audio without ADC

[Jesus Arias]

Hi,

This is a voice-quality audio digitizer built without an external ADC, it only requires a few resistors and capacitors.

Features:

- 8 bit resolution, 1 channel

- 9.375 KSamples/s

How it works:

The internal 2.4MHz clok is divided by 256 and the resulting 9375Hz square wave is presented at the "sqw" output.

An RC filter converts that signal into a something like a triangle-wave. The input audio signal is added to this wave and presented at the 'gate' input.

This results in a PWM wave inside the FPGA and its duty cycle is measured with an 8-bit counter.

The resulting value is sent through an UART transmitter (at 115200 bps). A capture for a frequency sweep is attached  (converted to MP3) 

This poor's man ADC can also have some distortion, but it is still well suited for speech. (If an audiophile quality is needed please put a tube in a corner of the circuit and pretend it does something useful ;)

Best regards

[charli va]

Thanks Jesús! a lot of useful information, thanks again!

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[Democrito]

When I listened to the MP3, the beginning of this song came to mind.

[Jo mo]

@ Democrito: concerning sound tunes, you have a very good Brain  Bram/ or ROM  :-)

@ Jesus: about this cheap ADC subject i was also looking few week ago about a similar solution but using  a differential pair input of our FPGA!

The analog substraction (adc in - fpgapwm out) is done by the input comparator of the diff pair.

In your solution Jesus the "substraction" is made by  a "superposition principle" of audio in and sqwave (pwm)  ( using R1,R2,R3).

it will be interesting to compare the results of both methods!

Any way, this is good reason, for me to make "differential pair" icestudio blocks for our iceIo collection (for ice40 an ecp5)!  I have so many things to do, ans so little time for doing them :-(   :-))

Again, thanks for sharing Jesus

Have a good night guys

[charli va]

Other thread that promise very interesting and useful :)

Tell us Joaquim when you compare the two methods!

Thanks a lot!

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[Jesus Arias]

Hi,

Yes, a differential input would make things easier, but it requires some specific cells (SB_IO for ICE40). And you don't have to worry about the pin hysteresis, that, in my case don't affect the signal too much while the input amplitude is low (when reaching saturation the output is quite bad)

And a Sigma-Delta ADC is way better than the simple PWM I presented, but more complex too. It would require:

- A second order SD modulator with two integrators that would imply two OpAmps. (first order SDs tend to get stuck into periodic output bitstreams and that's bad) I'm attaching an example using inverters instead of opamps (for a different clock frequency please scale the capacitors)...

- A third order decimator / low pass digital filter inside the FPGA. The simplest one would be a comb filter, with about 6 adders and registers (many of them about 12-bit wide)

In brief: It requires a lot of work while you can put an external codec and all your trouble is just the I2S interface.

Best Regards

[Jo mo]

yes, those simple ADC (like in your solution and mine), should only be used for low frequency signal measurements (like potentiometer movement, maybe up to 1khz) .  A bit like arduino ADCs

Above we need to care, for any ADC or DAC, about removing  the frequency contents above the Niquist frequency (sampling rate / 2).

And use a low pass filter (with the "highest order is better but more complex" trade off) !

and as you wrote it digital filter "in verilog " or analog filter (outside the fpga).

As you wrote too,  a codec like the one i bought 2 days ago(see other post ak4919 pmod) is the easiest "verilog coding" solution (includes digital filter for adc and DAC). 

But those filter are tailored (almost fixed) for a certain type of signal (in ak4919, audio signals max. freq around 22Khz)

So to summarize al this depend what we want to do with those ADCs.

Best regards

[Jesus Arias]

I tried your circuit, using an LVDS input, and it worked very well (better than mine ;).

I just want to mention that this was only possible after registering the input using the 12MHz clock. A very weird input signal was obtained otherwise that resulted in a bad performance.

wire lvds;
SB_IO #(.PIN_TYPE(6'b0000_01), .IO_STANDARD("SB_LVDS_INPUT")) lvds0
(
    .PACKAGE_PIN(LVDS), // LVDS is pin #2, (pin #1, implicit, is the negative input)
    .D_IN_0(lvds)
);

reg gate;
always @(posedge CLKIN) gate<=lvds;

I also routed the "gate" signal to a pin in order to look at it on the scope:

An FFT of the captured data is also included. Here we have a 300Hz input tone, the distortion is -32dB (a 2.5%), and the Signal to Noise Ratio is 40.7dB

A last comment: This time I'm also using a fractional clock divider in order to achieve a sampling rate close to the usual 11025Hz:

// Factional divider 12MHz x (241/1024) = 2.824MHz
reg [9:0]divi=0;
always @(posedge clk) divi <= divi +241;
wire ck2M8 = divi[9];

I think this is a quite simple yet practical ADC. And a very cheap one ;)

Regards

[Jo mo]

Beautiful test Jesus, Thanks a lot!

It has plenty of good extra info for us. For sure, we will use it when we will design:

- an LVDS input icestudio block (for ice40) 

- and of course a cheap, quickly implementable ADC block (no need to order an ADC part at mouser, we have all we need at home/inside the chip ;-).

Best regards

[charli va]

you are awesome! this weekend try it with the scope.

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[Jesus Arias]

A short video with a wave digitized with this contraption (LVDS version):

[charli va]

With a lot of good anxiety to try it!! :)

By the way, the icecream board looks good!

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[Democrito]

I loved the video. What a clean wave!

[Jo mo]

Really nice Jesus,

So you are measuring the signal that you inject with the red crocodile !?

What is the initial frequency of that sine-wave you are injecting?  300Hz ?

What is crazy is that the trigger of the measurement doesn't move at all ! even when you play with the freq of that sine wave !

In fact it, looks like if the wave was not measured, but generated by the fpga itself (tin that case he, of course , knows the start of the wave he generates, so it is will be easy for the fpga to "synchronize" de displayed wave)

But, if it is an ADC measurement of an external signal, it is surprisingly stable ??? !!!

Thanks, and have a nice start of weekend!

[Democrito]

Joaquim, I was also amazed when I saw that the trigger was stable and didn't even flinch.

[Jesus Arias]

Yes, the input was the red crocodile from a signal generator. I was measuring an 80Hz sine wave FM modulated (about 30Hz deviation and 2Hz modulation, I think)

And the trigger looks stable because I'm waiting for a threshold crossing before starting  the adquisition.

But the signal isn't so great, It has more noise than it should, and I think the problem is related with the dirty edges I got in the internal PWM signal. It seems the LVDS input is oscillating at a very high frequency when the two input voltages are close. An input register reduced this problem a lot, but not completely...

Well, it still requires more debugging,  but anyway, the visual feedback helps a lot in finding that kind of problems.

Regards

[Jo mo]

Hola Jesus,

Yes, we can see some artifacts on your video!

As you wrote the visual feedback is very good for debugging!

Looking at it picture by picture, we can catch quite some screenshots like this one.


we can see that part A an B are out of phase !
The cause are either shift1 either shift2 (in two "successive"?? plots )

What is interesting is that both shift :
- are starting at the same voltage level, ( in this screenshot it is at your trigger threshold (see horizontal yellow line), but in other screenshot it not necessary at the threshold level )
- are producing exactly the same amount of phase shifts (mean the two curves are joining again after the two successive shifts)!

Also open question:

- what really are those two plots on a same picture ? 

- Why the brightness of parts of the curves is different ?

Also sometimes, like in the next picture a curve is moving backwards (and again to join another curve)! 

Can it be a problem in the way we store (or get) the data from the buffer memory before sending it to the VGA screen?

Maybe to simply the understanding, it will help to make a video with no frequency movements (no FM) ?

I do not understand the reason of all this, but it "smells" like something simple (not like teen spirit :-)   ) !

Little remark, for sure, not related to the "shifts problem" : 

In your post with the FFT plot, you wrote about an usual 11025Hz sampling rate. You probably know about all this, but i write it has a "reminder"

This 11025Hz sample rate is well adapted to signals from ("0" to 5502.5 HZ) like low quality audio, human voice recording (max freq 4khz, we are not birds :-) ), telephony, ...
To acquire the full spectrum of what human ear recognize a 44 khz sampling rate is necessary.
And has we wrote above, in any case we need a "good" order of filtering if we want to reduce aliasing!
If we do not want to use a filter, or just use a simple first order low pass filter, we can also try over-sampling the signal to minimize aliasing !

Have a great Sunday

[Jesus Arias]

Hi,

Most of these strange frames were just that, artifacts due to being writing the wave data while it was already being displayed. You wont see them if the signal isn't changing. I solved that using double buffering (we need double the RAM, but it is still just 1KB, see the verilog sourde attached). And also now I'm waiting until vertical retraces (VSYN low) before changing buffers, so, whole frames are always displayed. With these changes the image no longer shows these strange transients.

And about sampling rate. We still have margin for a faster sampling rate, just multiply the clock frecuency by 2 or 4 and divide the capacitor by the same ratio. But for high quality audio we also need more resolution and linearity, so, I don't think this approach will work. (for 16-bit resolution the clock should have to ve multiplied by 256!)

Abe a nide day

[charli va]

Hi team! very interesting! I'm working on the new Icestudio features (constants, plls...) and I'm reluctant to try this XD as soon as I finish the rest, I'll join the sine party XD

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[Democrito]

This is a quantum-relativistic move into the past!

Please forgive me for this joke!!!

[Jo mo]

 @ Democritos:  yes:-))  and soon, Jesus will convert a seat 600, which will allow him to say hello to Neanderthals, and show them his fpga board of course :-)
 
 More seriously, congratulation Jesus !!,
 
 It is crazy what you can do with only about 50 lines of verilog code (the rest are useful comments), and using so little quantity of Fpga ressources ressources !

 It seams to me, that with this kind of application (custom adc + vga display), we are starting to clearly see the potential of FPGAs (against the use of microcontrollers)!

About the need of making the bit rate higher for CD quality, you are right!  

But if we just go to 10-12  bits and do a bit of interpolation, it can do the trick (without to much of resources usage increase) ! 

Plenty of room to play with, this is what is great !  And when i will have a bit more time, i will try making an icestudio block ! So thank a lot for sharing this beautiful verilog code with us !

[Jesus Arias]

:) :)

I don't really understand how that frame came to be. I hope with the double buffer these strange captures are gone...

[Jesus Arias]

>It is crazy what you can do with only about 50 lines of verilog code (the rest are useful comments), and using so little quantity of Fpga ressources ressources !
 It seams to me, that with this kind of application (custom adc + vga display), we are starting to clearly see the potential of FPGAs (against the use of microcontrollers)!

Well, these lines are only for the display controller and ADC, but the system I'm using also includes a CPU with some memory and runs an small program with the adquisition code (so there is a microcontroller in the end ;)

[Jo mo]

yes, Jesus, much better in this last video!
Only default remaining (sometimes, for a changing wave)  the display of the previous wave. can occur (simultaneous with the current wave)

Looking more carefully at your last module posted, i can see that the ADC itself and the orchestra conductor (micro-controller in your case, as you wrote) are not included in the module.
Still this VGA display is quite low in resources cost.

And Adding the ADC module and maybe just a state machine for the acquisition driving  (if not so many other think to do), will keep the total amount of resources very reasonable for someone which need a full cheap/simple "oscilloscope"!

To summarize,... Great/reusable work Man ;-)

Have a nice week!

[Jesus Arias]

Hi again
Let's me resume the features of these ADCs
The LVDS input version was finally stable. Probably my mess of wires was me main issue with its noise.
But it only run well with low input amplitudes. It seems to me that the input comparator has a limited common-mode input range, that is OK for LVDS signals, but not fot this ADC:

The single CMOS input, on the other hand has a weird saturation due to the pin hysteresis

But it allows for higer input amplitudes, and that ugly saturation can be avoided using a higher input resistor. This is the "tuned" circuit:



And, finally, let me attach a sound recorded using this circuit

Best regards

[Democrito]

Está genial Jesús, a ver si me pongo con este tema para experimentar, que nunca lo he hecho, ni con VGA. Por cierto la canción muy buena, especialmente cuando la canta Nina Simone.

[Jo mo]

Hola Jesus,

Those tests you did are really interesting!

About the LVDS option, it also has the disadvantage of using 3 fpga pins (compare to only 2 for your initial Cmos version).
If someone still finds a good reason for using the LVDS version, he can use signal conditioning stage before sending the signal to this ADC (dividing the amplitude by 2).
But he will loose half of the signal dynamics / loose 1 bit of precision with this 8bit ADC.

About the single input Cmos version (the one with which you made the audio test , if i understood right), the final result is quite good !

The only problem i can ear, his a little (hiss) /high frequency noise when the wave as a simple audio contents.

Like at the beginning of the .wav were we have a low freq instrument (maybe a double Bass)

In the joined video, we can see an FFT screen-record, took at that starting part of your audio sample.
In in this .mp4, i am cutting those high frequencies (by switching on and off), with a simple first order (cutting slope= 6dB/frequency doubling) low-pass filter, with a cutoff frequency of about 4khz.

But doing so we are also cutting a bit the higher frequencies of female voices,..

For me the best is really to increase the sampling freq for at least a factor of 2 and this 3 reasons:

1)- Having a sample freq of 11khz means that all the useful freq between 5.5 and 11khz are fully cut! ( as we can also see in the video).

The reason is that to record a wave, we need at least 2 sample per wave cycle(in this minimal case the shape of the wave is almost killed but a trace of the frequency of that wave is recorded)

picture found here

2)- The amplitude of those same cut frequencies is mirrored (by the 5.5 kHz "Nyquist mirror") and summed to the amplitude of the frequencies between 0 and 5.5 kHz!

picture found here

This is the reason why we have this hiss (that i am filtering in the video)

If we move the Fsampling to 22 kHz (or 44 kHz), it also moves the Fnyquist to 11 kHz (or 22 kHz ) and the mirrored frequencies will be much less.
Here are 2 more links about that subject: link1 ,  link2

3)- it seems to me ( but i may be wrong ) that a higher Fsampling we may use a bit less resources.

I am just quickly taking in account the fact that we will just need 1 or 2 bit less in the counter register, which counts the time between 2 successive samples to acquire.

What do you think Jesus?

And as you wrote, at the end of your last post, we can play with the input resistor, to get the best cutting frequency ( around final Fsampling/2 )

Big hug and have a great day.

[Jesus Arias]

Hi,

As you probably noticed I left the capture as a WAV file instead of compressing it into an MP3 file because that compression changed the hiss noise.

That noise I think is mostly quantization noise (we only have 8 bit), and maybe also some electrical noise.

With respect to aliasing, well, the sound I was playing was also a WAV file, that I resampled using "sox". It had a sampling rate of 11.025kHz, and it was already low-pass filtered by sox (and by the analog reconstruction filters of the souncard), so, it shouldn't have a noticeable signal amplitude for frequencies over 5KHz. The player file had 16-bit samples instead of 8-bit, although.

The input resistor can adjust the input range of the ADC. There is no filter there (It should, to avoid aliasing if the audio spectrum has high frequency components).

My clock rate was 48MHz / 17 = 2.82MHz, that divided by 256 results in a sampling rate 11.029kHz. I also tried fractional clock dividers with good results (if yout don't like to use a PLL). For a 22kHz or 44kHz we  need a higher clock frequency / smaller clock division, and also to replace the capacitor with a 22nF or 12nF value

Nice day

[Jo mo]

Hola jesus,

About that noise, i am starting to understand that you are right !

Also, In the double bass part that i was filtering, there was no reason to have on that bass instrument high frequencies creating an aliasing frequencies!

So as you wrote it should be a quantization error added by our 8bit acquisition!

About the passive component at the input, yes, i wrongly thinked that there was an low pass filter in all those R and C combination!
But looking more carefully at your last Cmos schematic, the only low pas filter (R1/C1) is for filtering the sq_wave output.

Remark: on the initial audio Cmos schematic, C2 was present and we had a highpass filter (C2/R3/R2/R1) and it as a cutoff freq of about 24Hz.(audio stuff/reduction of unwanted/uncontrolled infrabass sounds)
So, as you wrote on the title of the thread, we can use this first version ADC for audio signals.
But this initial design can not be use to record DC signals (like a potentiometer position) for this one, we need your second and last version of the schematic.

I just, see that in your second schematic you removed C2, i suppose that you made the last audio acquisition test with C2 removed?

Has you may imagine, what i would like to do in the end, is make icestudio blocks including (inside the block) a schematic of the component to use at this ADC verilog input.
And this for multiple type of signals (audio and DC).
So, When i get quite some more time, i will try to play with your Audio ADC design,:
- To try to reduce this "hiss" sound. maybe by increasing the resolution (12bit).
- And to, cover better the human ear frequency range, i will also increase the sampling freq following your advices! and add an external low pass filter! Because not all the input signals are pre-cleaned (as you did with your input audio signal)

And has you suggested me, i will need to use a pll to increase the system frequency ( x 16 for the 8-12bits move, x4 to for the 11khz to 44khz move)
So if i am right : my final ADC clock input will need to be 44khz (sampling rate) * (256*16) (resolution/possible results) === 180 Mhz.  I will shake the body of all my little Fpga logic gates :-)

Jesus those last sentences, i wrote are just a post-it reminder form me (for when i will decide to make those icetudio block).
So, do not waste more of your time on this! You already did a lot on this subject!

Just, if your actual adc verilog code change "a lot", since the one you posted in your first post, please, do not hesitate to put it here again.

Once again, thanks for sharing all that knowledge man, it is invaluable !

have a great day.

[Jo mo]

A little ingredient to add on the pizza :-)

I just found a very interesting document about this internal ADC subject (for low or higher frequencies input signals).

It is on the LVDS side of the force.;-)

Jesus when you did your test with LVDS input, did you rework the s_quare output to get out a kind of pwm (like the SAR (successive approximation) technique does in the above document)?

Or, did you find a way of keeping the generation of the fixed frequency (9375Hz) square wave as you started using for the Cmos version ?

Have a nice evening !

[Jo mo]

And on the for the Cmos side of the force :-)

searching a bit more on the web, i found that your technique look a bit like a "dithering",  adding a noise to an input signal to be able to use a 1 bit ADC (the Cmos input ) as a 8 bit ADC.

a)  input signal

b) a 1 bit adc reading the input signal

C) input signal +noise

D) a 1 bit adc reading input signal +noise

*

The only think is that in your case you are not injecting noise but a fixed frequency triangle wave !?!?

Can this be the "reason" of our "quantization" problem?

Here is a link about dithering audio for reducing quantization problems 

Sorry for the spamming, guys  ;-)

[charli va]

Nothing about spam, all this information is pure gold.

Thanks Joaquim for invest your time in sending us all of this information, i'm hope joining to the party in short :)

I'm reading tonight with very attention

Thanks again Master!!

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[Democrito]

All the documentation you provide is valuable. I have no idea about these things, but perhaps in the future, when I deal with this, your comments will be useful to me, and also to many people.

So good luck and thank you very much Joaquim and Jesús!

[Jesus Arias]

Hi, and excuse me for the delay...

Without C2 the ADC can measure DC voltages, like those of potentiometers and the like (if their output resistance is way lower than the input resistor). But, for audio capture C2 is very convenient because otherwise you'd have to add a 1.65V DC component to the input.The recording was done with C2 in series with the soundcard output.

And, regarding the document you pointed, this ADC is neither the SAR nor the SD versions stated, but something in between. Here we got a sample for each PWM cycle, while in the SAR approach may cycles are required while filtering out the PWM carrier before making the comparison for each bit, so, it is very slow. 

And the sigma-delta approach is something very different. In fact I tried it many years ago using a PIC microcontroller (http://www.ele.uva.es/~jesus/adsd.pdf). A first-order SD like the one shown in that document  seems to be doable, but first-order SDs aren't very good, mainly due to idle tones:

A SD converter generates a pseudo random binary signal at the output where the average number of ones vs the total number of bits is proportional to the input voltage. But sometimes the converter locks into a repetitive output pattern (idle tone) that degrades the performance.

Anyway, for the SD version of the ADC the LVDS input is absolutely necesary because for these ADCs the comparator hysteresis is also very bad.

And the digital signal we get still have to be low pass filtered, and this implies a good deal of FPGA resorces...

Have a nice day

[Jesus Arias]

He again,

I forgot about the dithering. The dithering doesn't reduce the quantization noise, on the contrary, the total noise is a little higher when dithering is applied. But it makes the quantization error to look like random noise, and this is usually more desirable than some weird artifacts in the signal.

Dithering is also more adeccuate for DACs. For ADCs the analog noise at the input is usually enough to make the quantization to look random.

Best regards

[Jo mo]

Hola Jesus,

No problem for the delay,  myself, i often take my time to think about the subjects and reply ! 

And after all , we are not paid here! ;-))  So let us be free, and have fun :-) !

Thanks for your document with the "pic16f84 adc" it is very interesting too !

An idea will be to make it work with a pic16f84 softcore!  

But looking about all we have seen in this thread, we will, most probably, be not very efficient in term of resources usage.

Unless, maybe, if we try adding digital stages (2th order aliasing filtering, dithering,...) in the chain.

Thanks for pointing out to this "iddle question" , i have never eared about it before. Or maybe at school 25 years ago, and i forgot about it :-))

This week end, i really need to concentrate in finishing a PCB (for other thinks), and then order it ! 

And next week, as i received yesterday my AK4619pmod interface  from Germany, i will start making it work inside icestudio (creating blocks) !

Then i will try to implement your ADC code and make some audio test using:

- your adc for recording audio 

- and the AK 4619 codec output (192KHz / 32bit) to listen to the recorded sample.

But as i am quite slow:-), this is a long way walk.. so guys, do not expect result, on my side,  too soon ;-)

A big hug and have a nice week-end guys !

[Jesus Arias]

Hi,

I tried the Sigma-Delta solution, and while it is still awaiting more test about its performance I can positively say It is a lot better than the PWM converter. Here is the schematic:

An LVDS input is needed. It requires 2 pins in an lvds comparartor because  SD converters don't tolerete hysteresis (otherwise a single CMOS pin would be enough). I also connected one pin to a constant Vdd/2 voltage instead of the signal input in order to keep both comparator pins around this voltage (lvds comparators don't work well if the input voltages are too high)

And this is the block diagram of the digital decimator / low pass filter. All variables are 15-bit wide, except in, that is only 1 bit, and out, that is truncated and saturated to 12 bits.

The sd_adc module fits into 160 logic cells and can run up to 100MHz

One interesting feature of SD converters is they don't need any filtering in the input (unless we have some signals above 1.4MHz ;)

My preliminary tests were very good, but I was looking only into the 8 MSBs. I'm expecting about 10.4 effective bits of resolution with a sampling rate of 22.050 kHz, and way less distortion than in the PWM converter, even when taking into account the effect of the idle tones.

Regards

[Jo mo]

Hola Jesus,

This one, looks really compact for what it does (40 lines of verilog code, and no Dsp blocks !!!), This is black magic !!!! :-) !  i will need to study this short code!

I like this input circuitry! If am right we can have at the input:  - vcc/2 < Vin < +vcc/2 , very good for ac signals (like audio) !

Can you quickly remind us how you are recuperating the acquired data? ( using a dac as output from the fpga( connected to audio speaker), or sending the digital values to the computer(with a soundcard playback))?

Thank you again a good luck for the test !

Have a great day!

[Jesus Arias]

Well, the input range goes from 0 to 3.3V, for audio just put a series capacitor at the input.

And I'm still struggling to get the data out of the FPGA. My idea is to use a serial port, while meanwhile I'm displaying it in a VGA screen (only 8 bits)

[Jo mo]

Ah yes, you are right for the input range (i made a mistake when i looked at the schematic). 

So,.. perfect!  we can do DC acquisition (and AC just by adding a cap as you wrote!)

For the data out, :

- with serial port, we are hitting the limits if we try doing it real-time: (12khz 12 bits   vs   1 bit 300kbps)

If we limit the time of the recording (maybe just 4 seconds), we can use a buffer (1Mbit) (before sending it to serial TX pin).

Then, on computer, we need to find the good software to get this serial data and "convert-it" to an audio data! serialtest.exe may help (good for plotting and recording/saving data)

- If you have in your drawers a DAC it may be, easier!

Benitos made a verilog i2c driver for UDA1334A but if you have another dac, i am quite sure that we can quickly find a Verilog code for it on the web (github,...)

Than you can send this to your sound-card micro input !

We just need this dac to be a bit more precise and fast than the measurement we are doing(eg for a 12bit/22khz,----> 16bit/44 khz dac, and soundcard input should be fine)

I know, you know all this and even more :-) but if one word of this message can help you find solutions, i will be happy ;-)

Hug and have a good evening

[Jesus Arias]

Yes, I'm transmitting at 1.5 Mbit/s, two bytes per sample, and my PC is losing data time to time. That's a pity, because the captured waves look great on the screen, almost noise-free.

[Jo mo]

Yes, beautiful sine wave!

Do you by chance ave a teensy board ( 3.2, 3.6, 4, 4.1 ) ?  It has the ability to take an i2s input (from STL5000 chip an few others ) and send it to usb.

And it will berecognise by the computer has a sound card!

So we can see the sound with audacity, or other...

So in the fpga side, we need to send our 12 (or 16) bits to a verilog i2s transmitter and this one will mimics the "ADC" part of communication of one of the teensy compatible chips:

• STGL5000
• TLV320AIC3206
• AK4558
• WM8731

Eg: for the last one here is a link to a verilog code

and we connect this i2s fpga output to the teensy.

The advantage of such solution is that, (like for your 1.5mbit serial transmit) we eliminate two D-A, A-D conversions. the dac (out of the fpga), then adc (computer sound card).

But it require a teensy (with no audio codec) and some work on the verilog i2s transmitter :-(

Regards

[charli va]

Good night ! I’m joining to the party ! For today i’m finishing prepare my setup, little messy but at the ends works perfectly (i use potentiometers to have some range to play at the input step)  and start to learn  Lvds io blocks, i'll try to join this knowledge with the usb high speed peripherials in short, this could be a very good training.

For today not wait nothing useful for me XD i need to read and think all about your are sharing, that is awesome.

Thanks a lot folks!

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[charli va]

I have ideas to the trasmision step, i'll try to have in a couple of days. The teensy solution is cool!

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[charli va]

Jesus, what uart chip have your board?

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[Jesus Arias]

it is a CY7C65213, a serial to USB converter of the  CDC/ACM class (not like FT232s that are vendor specific)

But I think the problem is in the PC and its drivers, (Lubuntu 22.04) The CY chip has a 256 byte RX FIFO...

[Jo mo]

Nice start, Charli charli welcome to the party ;-)

For the uart tx to computer! Again even if we manage to do it!  Then what software can we use to convert (realtime/or not) this transmission to a computer audio format?

Another possibility to transmit numerical sound to computer is SPIF/TOSLINK
- fpga to spdif is not a problem plenty of verilog available but then we need an spdif to usb interface for the computer.
something like this!

Then if you have no optical cables and plt133 connectors in stock, you can just wire from the fpga output a cable with at his end a 5mm led and insert it in the input optical connector of the above sound-card

remark: Using another color for the elastic holding the led in the connector will do the job too ;-))



While looking for digital sound to computer solution, i found something not fpga related but:

CAUTION THIS IS SOUND AND DISPLAY DIY PRON :-)

https://github.com/sdima1357/stm32f401cdu6_Audio

In the 3 videos there are nice display! The movements of the nail is almost perfect in the third video!

Again this is not useful in our case, we need an usb numerical sound input to the computer (not an output)

sorry for this little out of subject !

have a nice day!

[Jo mo]

I forgot to write thaht teensy also dors spdif to USB. So no special soundcard needed if you have one!

Juste connect an fpga pin to the rigth teensy pin!

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[charli va]

Hi Jesus! First of all, thank you for opening this thread because it is being very fruitful and interesting, thank you!!

To continue, I am entering into this topic of lvds io, it is the first time I work with it but something does not fit in your latest scheme, is the position of lvds+ and lvds- correct? When studying the ice40 documentation, it seems to me that Vin should be connected to lvds+ and the feedback signal to your lvds-, but in the design it appears the other way around, I may have some misconception or I have misunderstood something, or could work in both ?,t if could you clarify this for me, I would appreciate it, I like to understand the theory of things well before putting them into practice.

Thank you so much!

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[Jesus Arias]

Hi, Carlos,

The connection of this image will also work, but only if the input voltage is low.  The LDVS comparator do not operate well if the inputs are close to 3.3V (I found it the hard way ;) With my connection both input are around 1.65V and there is no problem. So, in the end that circuit was a workaround

[charli va]

Thanks Jesús!, i'm working with a very low voltage too! i'm starting to connect things, i hope have results soon.

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[Jo mo]

yes charli both circuits work but not has well :-) !

The difference is in that:

- in the original ADC circuit the "comparison switch" of appends close to Vin voltage level. So comparison switch at any voltage from 0-3.3V

- And in the Jesus (slightly more complex schematic) the comparison always appends at the same voltage level (Vcc/2 = 1.65V)

This voltage is a better use of a comparator!

And in ice40 datasheet they also recommend a Vcm = VCC/2  see page 3-7

The only think is, that due to this difference in circuit schematic, the feedback signal logic generated by the fpga should be slightly different !

Have a good evening guys.

[charli va]

Thank you Joaquim and Jesús! I'm experiencing "ecstasy" XD

First try and it seems to "work", wooooouuu!!

I'm working with this little oscilloscope that has a signal generator and could run at different voltages. To start, I set it to 433 Hz and 2 V amplitude

Channel 1 is the adc output :)

At first I'm playing with Jesus' scheme, I needed to increase the capacitor because with the initial value of 10nF it didn't work, I increased it to 1uF (I'm traveling and I don't have many resources here XD). with this it seems to work better (could be that the first one has broken, I will try it at the end of the week at home). When we have a complete example I would like to experiment with the analog part to incorporate audio directly.

First I'll try to work on sending to PC, these exercises are very interesting for me, they mix up a lot of things I'm working on... so thanks again guys, I love when things converge.

At the moment I have a lvds block for Icestudio and Jesus ADC in one block, I want to mount the vga scope block but I wanted to modularize it with the previous vga example to start having reusable blocks, I have to study "the sorcery of Jesus" No I know if I can say much more today, but I'll tell you as soon as possible!

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[Jo mo]

Looking a bit better at that datasheet page (i linked), i see that in fact ice40,  LVDS25 max in put is 2.5V  (and not 3.3V)

So the ideal reference is 1.25V and not 3.3/2. 

But using 3.3/2 (if it works ok, has shown Jesus) is better because it allow a wider input range (of 0 - 3.3V) wich is also the max range of the feedback output (that we can generate)

[Jesus Arias]

This is what happens with the original circuit. It only works well if the input voltage is around Vdd/2

[Jo mo]

Hola Charli,

Your scope reading looks like a 1 bit ADC ?

This change of capacitor is way too drastic 1uF and 15kohm means a lowpass filter with a cutoff frequency of

= 10.6Hz

instead of 1061 hz with the 10nF value !  (which is already too  big for audio signals)

So all the frequencies above 10.6hz will see a big reduction of their amplitude! 

Do not hesitate also to join your *ice files, it can help understanding what you are doing !

Have a good night !

[Jo mo]

yes Jesus,

I think we can forget about that first LVDS schematic ! 

Its is not good for DC aquisition where we need the full range 0-3.3V (like for a potentiometer reading).

it is only good for small (about 2Vpp) AC signals(and only if those are offset-ed by 1.65 V )

So let us concentrate in your last LVDS schematics which also correspond to the fig 5.2 in this lattice doc !

Good night my friends!

[charli va]

I know!! but I did some math and thought turning it up a bit might work and I didn't have any other capacitors, it probably wouldn't work with a sound source. Anyway, if you want to check it out, I attach the strange Icestudio design, the electronic part I will improve over the weekend with more components, here you have much more wisdom than me, all the comments and advice that you can think of to prepare a good stage At first they will be great.

In the end I couldn't resist and have been working on this a bit more, I have included a dac in the code block, the output signal (yellow) against the original 433Hz to the 2V wave source (green):

The image of Jesus seems better than mine, but step by step (it doesn't look bad apparently)

If you want to play with it, fantastic, Joaquim, in short, we can also use all these blocks to test the new function to make code compatible between boards (I will finish it this week, it has taken me more time than expected due to family matters these last two weeks but I will I'm practically finished).

My idea in the next few days is to prepare the transmission part so that we can compare alternatives: vga, serial port... and whatever comes to mind XD

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[charli va]

I forget the .ice sorry team!

[Jesus Arias]

Yes, 1uF is way too big. Now I'm using 1.5nF

Regarding the capacitor, Ideally big values are better because we are replacing an integrator with a simple RC, and integrators have their pole at 0Hz.

But, in the real world noise is also present, and a too big capacitor means very little amplitude at the comparator input and any noise will ruin our signals. So, some trial and error had to be done.

Finally I managed to get some data in the PC, by means of first storing it in an external SRAM and then sending it slowly to the PC

Here we have a 10Hz sine wave (samples are 12-bit wide, but resolution is less) It looks perfect

But it isn't. After a curve fitting to a sine I got this difference (X axis is the output level):

An ideal 12-bit ADC should have the error bounded to +- 0.5 LSBs, so here our effective resolution is way less than 12 bits. This graph also shows the non-linearity of the converter, mainly related to the effect of idle tones, and the excess noise when the input signal is near the input limits, a well known problem for SD converters.

And now the same signal in the frequency domain after a Fourier transform. Here the signal to noise ratio was about 51dB. This gives us an affective number of bits of ENOB=(SNR-1.76)/6.02 = 8.2 effective bits.

This was much less than the 60+ dB of simulations, meaning real-world effects are a pain. But for a bunch of resistors and a capacitor we can't ask for the Moon. (I'd wish my old cassette tapes could have 51 dB of SNR ;) 

And another capture, this time only 3 second long (I got no more RAM for longer recordings)

Regards

[charli va]

tomorrow i'll try to find in somewhere a little capacitor, anything for a nanofarad!! XD

The recording sounds really good! the sounds remember my a vinil disc.

What do you use for the plots ¿gnuplot or octave? Tomorrow i hope have an alternative to transmit better, i'll check the datasheet of your uart and shoud be works until 3Mbits/s.. I'll try to export the verilog code if you want to try.

Thanks  again!

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[Jesus Arias]

Hi, Charli

Respect your Icestudio design:

- Remove the "gate" register. Between 'lvds' and 'fb' there should be just 1 flip-flop

- The clock should be 2.8MHz. I'm using a PLL with 48MHz divided by 17. This gives a sampling rate of 48MHz / 17 / 128 =22058.8 Hz. If you are using the crystal input of the Alhambra you can divide it by 4 and run at 3MHz

- I don't know what kind of signal you are generating at the "dac_out" pin. For an SD DAC you'l need another circuit...

[charli va]

Hi Jesus! ,  oh my god! with the emotion i dont think in the clock XD thanks again, tomorrow fix and test all of you indicate.

For the sd dac circuit i'm using the circuit in the first schematic ( a capacitor and resistor) but with a 10nf capacitor (appears one, bigger probably)

A lot of thanks and sorry for this entry like an elephant in a china shop ( i don't know how is in English "cacharrería" and google translate as this...).

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[Jesus Arias]

I used "gnuplot" for the cirves

[Jo mo]

@ Charli thanks for this first icesudio design!

@Jesus, thanks for this beautiful test.

+/-16LSB of error means we are loosing 4bits so we have a very good 8bits (22khz) ADC! 

Has i am a bit more concerned about the frequency contents (than with the resolution, even if they are a bit linked as you wrote) ;-) ! 

I compared , by ear and during 5 minutes,  this last 3 sec sample to your first audio sample and it seams to me that the "hiss" noise is much less audible in this new sample!

For me, this result you got is plenty sufficient for a ' free DIY fpga ADC'.  So now, with Charli we just have to convert it to icestudio blocks!

And has you wrote Charli, If we find a solution for making a block work for ice40 and for ECP5(primitives), this will be a killer function ! ;-)

[Jesus Arias]

Hi, Charli,

Let me show you an SD DAC I used some time ago. Here the input is a signed 8-bit value, I have to resize it to 12-bit, but meanwhile it can still be useful for debugging. For unsigned values just invert the MSB of the input.

//----------------------------------------------------------------------------

//-- Modulador Sigma-Delta de 2º orden
//----------------------------------------------------------------------------
// En simulaciones se obtiene una relación Señal/ruido de 74.8dB para una
// sinusoide de amplitud máxima, aunque la distorsión está en -53dB ya
// que la sinusoide estaba cuantizada con 8 bits.
// Esto nos daría un máximo de 12 bits efectivos si ampliamos el número de bits
// hasta los 13 bits en la entrada y 16 bits en las variables internas.
// (La aritmética necesita 3 bits más que las muestras para evitar
// desbordamientos)

module sdmod(
input clk, // alrededor de 3MHz, no crítico
input [7:0]in, // 8 bits con signo
output out // bit de salida
);

wire [10:0]err; // Error de cuantización
reg  [10:0]e1=0; // error del ciclo anterior
reg  [10:0]e2=0; // error de hace 2 ciclos
wire [10:0]x; // entrada (tras extensión de signo)
wire [10:0]y; // resultado del filtrado
wire outp; // bit de salida
reg out=0; // salida por registro (para evitar retardos variables)

assign x={in[7],in[7],in[7],in}; // Extensión de signo de la entrada
assign y=x+{e1[9:0],1'b0}+(~e2)+1'b1;  // y=x+2*e1-e2 (2 sumadores de 11 bits)
assign outp=y[10];                     // salida = bit de signo
assign err=y+(outp ? 11'h760 : 11'h0A0); // Error de cuantización (sumador de 5 bits)
  // Fondo de escala en 160 para no saturar
always @(posedge clk) begin           // Registros
e1<=err;
e2<=e1;
out<=outp;
end

endmodule

Also, if no LVDS pin is available (like for ICESTICK), we can still try this circuit:

Here I'm using an external gate to hide the effect of the pin hysteresis. Now, the center value is no longer Vdd/2 but depends on the actual gate threshold. Any gate without hysteresis will work, the 74HC00 was the one I tested.

[charli va]

Thanks Jesús! i'm reworking the design and send you later, i'll try to understand how my portable oscilloscope doesnt' work well, i'm not sure if it's broken or if chatGPT has posesed it and  started to infer signals that doesn't exists XD today i'm go crazy with it since your emails from yesterday.

The other circuit sounds promissing, i think we lead to ruin at the adc/dac industry XD

I hope send you more advances soon.

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[Jesus Arias]

Hi,

This time I think I got it finally right. Instead of using an external gate to act only as a comparator, lets use the gates for a lot more and build a second-order sigma-delta. Here is the circuit:

The inverters must be of the HCU type (U for unbuffered. HCs or HCTs won't work), and two of them are acting as Opamps. Well, a very bad opamps BTW, but good enough for this circuit.

Now, we get better specs:

- 44100 Samples/second

- 64.3 dB of SNR, 10.4 effective bits

- Less distortion, no idle tones:

But the filter now has to be of order three, and it requires 289 Logic Cells (fmax = 76 MHz)

And I found a way to download the data through the serial port: Instead of sending two bytes each time a new sample is converted, I store them in a 64-byte buffer, and, then I'm sending the whole buffer without idle time between bytes while also capturing the samples that are converted during the transmission for the new buffer. 

So, now I can include a little longer capture.  

[charli va]

The test is awesome Jesús! i need to buy some 74hcu04 to try it.

I'm working on it but i don¡t have successful results now.

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[charli va]

I'm slower than you Jesus, but I'm starting to have some results (bad but some progress).

I'm fixing the issue with the scope (I updated the firmware two days ago and it seems to have bugs... I'm rolling back and it seems to be working fine again and I can take measurements with confidence :)

I have corrected the clock by implementing a clock split. When everything works, I'll try pll to compare the results.

The calculation of the new clock has been: (12Mhz/(16bit samples +1))/11Khz*2. = 32
 
A question Jesús, Joaquim, if our ADC is 12 bits, why do we calculate the sampling rate around 16? This has me confused.

I am working on the transmission part and I have not finished it 100% but the progress is very good. I'm evolving the icestudio serial terminal to dump data to a flat file, then it can be opened with audacity for example to import and convert sound. Later I will try to do the entire process without having to go to audacity.

At the moment I only send 8 bits (the LSB of the adc comes out) but tomorrow I think I will have the module working to transmit 16 bits without problem.

At the moment the module reaches 960kbps, but I think I will reach 3Mbps and thus make the most of the uart and optimize brams. Tomorrow I will finish it and send it to you so you can try it.

This is my first album XD, much worse than yours but it is a small step and above all it has helped me validate the issue of transmission and saving. It's supposed to be a pure 433hz tone XD between bad capacitors and 8-bit cuts...better not to talk XD

On the other hand, I am playing with the DAC, tomorrow I will try the last one that you have proposed and that way we can compare results, but until the weekend when I have access to the passive components I will not be able to test it well.

So come on, hugs team! This is getting very interesting and the results that are coming out are impressive. Thank you all very much for sharing all this.

[Jesus Arias]

Hi, Charli

Clock rates are (for the first SD): sd_clk = 22050Hz * 128 = 2.8224MHz

You can use 3MHz (12MHz / 4) and your sampling rate will be 23437.5 Samples/s (a 6% too fast, not too much)

The 1/17 factor has nothing to do with the number of bits. It was my way to get a sampling frequency close to 22050Hz: 48MHz/17 = 2.8235MHz (BTW, in my case the PLL ran at 96MHz, and from there I got also a 32MHz for the video controller)

The SD filter is averaging 128 1-bit samples for each 12-bit output sample

The last SD (2nd order) averages 64 1-bit samples for each 12-bit output sample, so, it gives 44100 samples/s with the same input clock of 2.82MHz.

The SD filters are in fact moving averages (also known as Comb filters for  their frequency response). Well, a 2nd order filter is an average of another average, and so on.

Nice Day

[charli va]

Thanks for your explanation! Now all is clear , i’m needing to study some sígnal processing forgotten from the university days, Thanks a lot take time to explain it.

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[Jo mo]

Ok, Jesus this time you are really playing with analog electronics :-)  Congratulations for this one, it very good !

It is great to have multiple options (useful for multiple user, with their multiple needs) :

- a simple one ( with low external hardware and fpga resources use, lower quality ADC)

- a sightly more complex one ( with a bit more external hardware and fpga resources use, higher quality ADC)

remark: for external filtering, if we need to use a not so current IC, we can also put an amplifier (TL072, TL074, LM324 )

In this last audio sample you posted, we can almost not ear a noise ( it depend of the quality/precision of our listening device )!
But, just for curiosity, there is a clean little tone (sine) at 1379 hz and at his following harmonics(2.8, 4.2, 5.6 khz,...).

In the joined video, i filtered just the main + the first harmonic and the silent at the beginning of you sample is really quite silent!

Do you have an idea of where this tone comes from ?

Also, we have a little dc component, not being a whale, I cannot ear it! :-)

But in an "amplifier point of view", removing it (with a capacitor in serie as you already wrote), will help to reduce saturation problems in the loudest signals !

@Carlos: congratulations for your last tune! For the name of your future Album i have an idea: " lounge music for the bats" ;-))

Have a nice evening guys !

[Jesus Arias]

Hi, Jo

The tone you mention is being generated by my PC. You don't see it anymore when the converter is disconnected from the soundcard. I also found another tone at 60Hz that was a bit strange here in the 50Hz World, until I realized It is the vertical retrace of the VGA! So, I'm catching some electrical noise around (maybe due to a ground loop?). This 1370Hz tone is only 3LSB peak to peak, and I have no clue where it can come from... Funny things from the analog side :(

And the DC component depends on the voltage threshold of the gates. In my case waveforms were a bit low (Vth<1.65V), and I resorted to add a 220K resistor between ground and the input of the first gate to raise the DC baseline a little.

[Jesus Arias]

I forgot about the amplifiers. I like the TL07x, but they have to be powered with +-12V, or the like, and these voltages are a pain to generate. The LM324 can run with 5V or even 3.3V, but its specs are... lets say it softly, not very good. The opamps I find more interesting now are made by Microchip (yes, the same company as the PIC uC), like the MCP600x (1MHz) of the MCP628x (5MHz). These are low voltage, rail-to-rail, and cheap ;)

But I don't think we need much filtering because the input sampling rate of the SD converter is 2.8MHz (the output sampling rate is 1/128 or 1/64, but that's work for the digital filter) , so, a simple RC network would be enough to remove any frequency above 2.8MHz - 22kHz.

El jueves, 30 de noviembre de 2023 a las 19:03:46 UTC+1, joa...@gmail.com escribió:

[Jo mo]

Hola Jesus,

Thanks for your precise replies, it a pleasure to read as usual!

For the amplifiers, the TL07x family, was used a lot in audio applications, where the important freqs are limited to a small range (10hz-22Khz). All the rest can be killed/or not as we do not ear them :-).

I will say, we just need to care a bit about (22khz-50khz) in the aliasing filters case, Nyquist....
Maybe, that family, was chosen by audio guys, mainly for his "low noise amplifier" type characteristic !

For his powering, yes of course, we have to adapt our schematics to the voltage range of the signals signal which are passing trough!
And looking in the data-sheet, (apart from the m serie) the TL07x can be powered almost by anything :-). (eg: see also the link for the filters i put on my last post )

But you are right, we can not use the TL07x for our ADC application. And this at least for 2 reasons:
- they requires at least 4.5V between V+ and V-  (the VCC 3.3V of our FPGAs, is not sufficient to power them )
- for our cheap ADC, we are using the full range of voltage (0-3.3V) for the input signal to be acquired. And as TL07x are not rail to rail, they will "saturate" de voltages close to 0 and those close to VCC3.3V.

I did not know about the MCP600 family, but i see that it is also used in audio. So to be saved in my brain Rom memory :-) !

About the use of the an external analog filter followed by a digital filter (3th order) for doing the "same think"( low pass filter with fc=11khz ), i also thinked that it was a bit "redundant" ! 

But this is a matter of trial, if the effect of both filters are cumulating well to get a better cut of of those high frequencies! why not !

If not, we can just remove the one which has almost no effect!

Have a good night/or day :-)

[charli va]

Hello my friends! I'm working these days on things related to this and I'm making progress.

I now have a 3Mbps uart up and running, I've been testing on several computers (running Linux and OSX) and it seems to work fine on all of them. Tomorrow I will send you the Ice design and the Verilog code so you can try to validate it.

I am modifying the Icestudio serial terminal to allow data to be dumped into files encoded in 8 bits or 16 bits, the sending is done byte by byte, because in 16-bit packets the errors increase rapidly when we increase the speed), in the serial terminal , forcing the stop bit a little longer, works without transmission errors up to 3Mbps, this is the limit without special chips or cables. In a couple of days at most I will send you the code so you can try it.

Now I have a doubt because the supposed sound I am recording is not correct but it has improved a lot (now it is a pure tone without noise but lower than the original).
I checked the passive electronic stage and now it seems to be fine, the clock for sigma delta is now 3Mhz (I attach the clock generated to work as input of the sigma delta block):

I want to discard that the problem is the imported audio from raw data, Jesus, how do you convert the raw data in wav? i'm using audacity but the options that appears not appears to be correct (because theorically i'm dump unsigned 16bits that contains the 12 bits sample, and the sample frequency set to 22100Hz

Do you use other program? or what options suppose to be correct?

On the other hand, when pure tone works, I'll try it with music. What do you recommend for this case as an amplifier circuit for the input connector if I have a very low voltage, for example, if I wanted to test with a cell phone headphone output, I think the signal is around 20 mv. I have seen several circuits but I wanted to ask you if there was one that would fit better in this case that we are analyzing.

Thank you both very much for giving us all your experience on this topic, I'm learning a lot these days and I'm loving getting back to all this analog electronics.

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[Jesus Arias]

Hi, Charli

I used sox to generate the .WAVs:

       sox -r 22050 -t u16 -c 1 data.bin audio.wav

And It can be used also for changing the sampling rate:

      sox -r 23437 -t u16 -c 1 data.bin -r 22050 audio.wav

The cell phone can generate a lot more amplitude than 20mV. It can easily be up to 1V peak to peak, so, I don't think you are going to need any amplification.

Another tips:  put the 12 bits aligned to the MSB side of the 16-bit words, and, if you want a signed value just invert bit #15.

[charli va]

Thanks a lot Jesus!! the command works like a charm!!

The tone is not the correct but is very near and the sound "sounds" clear without noise  around (is the same that the last day). Tomorrow i'll play shifts and move the MSB and eview all to try to find where is the error and test the different DACs proposed to test the output sound.

About the sound source, i dont work never with analog sound and i thought that should be necesary "up" the levels, i'll try and tell you!

Thanks again!

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[Jo mo]

Hola charli,

Yes your sample sounds better

But it is richer in frequencies than a simple sine wave! 

In fact we can ear a 160Hz square wave  (and with a big dc offset close to the minimum of the measurement range)!

Maybe to get rid of the DC offset,  you can add a capacitor in serie at the input of your signal! This may help understand if your square wave is due to a saturation on both sides of the voltage range.

But this (negative) DC offset is so big that it will be nice to understand first why you have it (schematic problem?, verilog, ...?)!

I encourage your efforts on the work of Jesus's adc+Dac !

On my side i finished today my pcbs an ordered them. 

So now i will:

- Try understanding a problem i have with my car ( pwm controlled :-) EGR valve, and a mysterious position sensor on that valve)

- and be back to icestudio !  I hope, i will soon join the effort on "cheap ADC", who knows ;-)

Have a good evening guys!

[charli va]

Hi Joaquim!!! i'm very interested in learn around this ADC stuff i'm work basically with digital parts and my knowledge of analog electronics is lower but i want to learn and i'm very  gratefully for boths because this thread  has been my excuse to take your hand and start :), now i'm checking for some books to remember university days class and understand exactly what's happens in each step. i'm very intersted in analog electronics for future projects and ideas and never have a "good excuse" to take it, this is the moment :)

About the  tone, i know this is wrong, i'm trying to understand where is the error  ¿the first electronic step,  lvds, verilog?  step by step... and exactly the tone is generated around 160Hz and with a lot of other frequencies around  as you  tell:

last days i'm working in the telemetry and the icestudio serial term, in short i'll make a push with the new features (serial temrinal and generic constants,etc), i think you like a lot and hope could be useful, this week i'll try to  fix my ADC problems, then i'll try the next Jesús  ADC without lvds .

The idea when all of this thread are clear is make a detailed post with the resume, blocks etc count with you! i think could be very interesting an analog collection :) for music or other stuffs.

Maintain us informed about your car and pcbs!!!

Enjoy!!!

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[Jesus Arias]

Hi,

That low amplitude and big DC offset appear because the 12 bits of the ADC are on the LSB part of the 16-bit samples in the WAV file. Put it on bits [15:6] and this will be solved.  It is a digital issue, not an analog one.

But the signal looks like a plain rectangular wave. Maybe you have the two comparator inputs interchanged? If you are using the fist LVDS comparator the negative input is pin #1, and the positive is pin #2 (I'm using actually pins #9 (-) and #10 (+) in an ICE40HX4K board) Notice that if this is the case it can be also solved by removing the inversion in the 'fb' signal (it may be a simpler fix than to desolder wires ;)

Regards

[Jesus Arias]

Sorry, I should have said on bits [15:4]... mistakes happens...

[charli va]

Hi Jesus and Joaquim! i'll send you the next experiments:

1) I'm increasing the source signal voltage, because i think at yesterday test will be very low and for this the output signal are bad and appears an square one, i'll increate to 2.5V of amplitude for the test sine wave, with this the signal appears to be better.

2) I shift 4 bits to put 12 bits to MSB (the signal appears better but was still wrong), i  attach two pictures,   first without shift bits and next with 4 bits shifted (better):

16bits= 0000+12bits

16bits=12bits << 4 ( Picture A for the next) (attached as wav);:

3) To discard that lvds inputs could be swapped, i'm "swapped" the current setup and test and  i think all appears to be ok because if i swap the current setup, we are obtaining an square wave:

4) Spectral analysis of Pictura A wave contains a lot of frequencies (641Hz is the pure tone emited):

With the scope i take the next pictures:

a) The source signal (yellow)  and LVDS +(green) (pin 2 ice40 =  D0 in alhambra II)

b)  The source singal (yellow)  and LVDS - (green)  (pin 1 ice40 = D1 in alhambra II):

c) The source signal (yellow) and fb (green)

Is the first time i'm working with LVDS and sigma delta and i don't know if the curves fits ok.

Thank you very much in advance for joining me in this.

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[Jesus Arias]

Looking at your scope captures it seems to me the connections are somehow wrong.

- Pin 1 (LVDS-) should stay flat at 1.65V (here is the same as Vin)

- There shouldn't be negative voltages at the input. Please, increase the DC level in your generator, or put a capacitor (~1uF) in series with Vin (better idea)

[charli va]

Tomorrow i'll check all the components, the connections, in the mesh of cables, appears to be  well but i have the  sense that something goes wrong in the circuit from the beginning.

Your intuition is awesome Jesus, i can't upgrade the level of the input signal, my travel scope only is capable to generate signals to 2.5V max. and now i don't have much more capacitors here, i'm connecting in parallel all of i have now and in group sum ~0.5uF with this capacitance:

1) LVDS+ experiments a radical change, the signal very clear compared the previous one.

2) LVDS- is not flat, but slower than previous one (trend to zero):

the result signal starts appear a sine wave!!!! great!!! 

tomorrow i'll try to look for some capacitors for the correct values and i'll replace the circuit to discard the breadboard is broken.

Thanks a lot! a big huge!

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[Jo mo]

Hola Charli e Jesus,

Yes, this +500 mV/-600 mv "square" wave on lvds - is not stable enough!

Theoretically, the input current of the pin can be +/-10uA. 

Across the actual 10 kokm resistor it can give a square wave of +/- 100mV  on lvds-. 

It is not the ~ +/500mv you measured, but maybe we can try first replacing the two 10kohm resistors by two 100ohm resistors !?

Also on this lvds25 datasheet extract the, the the recommended Vcm range is 1.25 +/-0.3v,

To stay in those limits should n"t we move slightly our reference point from 1.65V to eg 1.50V ? with the following divider

Of course, if we do this ref. point change, we will need to adapt fb to output at his maximum only 3.0v "pwm or a like" instead of 3.3v (or change a bit one of the two 15k resistor value)

have a nice day!

[Jesus Arias]

Hi, Jo

The Vcm=1.25V you found is for a pin supply of 2.5V (typical for LVDS signals). But on our boards Vccio  is always 3.3V, so, Vcm should be close to 1.65V.

I also searched for that table on the ICE40 familly manual, but I missed it. These comparators have a quite limited common mode input range, only 0.6V. Well, they were intended for LVDS data, not for analog signals ;)

And Charli's waves look bad. Both LVDS- and LVDS+ should be flat. LVDS- perfectly flat, LVDS+ also flat but more noisy.

Regards

[Jesus Arias]

Another simple test is to take a look to the FB signal. It is like a random digital signal. But if you filter it with a simple RC (100Kohm plus 1nF for instance) you should get back your input sine wave (well, inverted and with some delay due to the filter):

[Jo mo]

Hola Jesus, 

yes i see you are right about VCCIO=3.3V. so lest us keep the reference at 1.65V!

But what about trying to minimize the effect of the input current on the lvds- pin? We should have up to +/-10uA (maybe a bit more under 3.3V conditions).

And if yes, should we do something also for the lvds+ pin?

In charlie's scope plots, we can also see a phase shift between lvds+ and lvds- signals. So maybe a reason of his big half sine phase shifts on his aquired wave!

So a matter of having the rigth RC filter values ?

See you later, i am out for few hours guys ;-)

[Jesus Arias]

Hi Jo,

I measured the input current when in LVDS mode at 0.000 mA, no reading at all in the multimeter. (but I measured about 40uA for unused CMOS inputs, probably due to pull-ups)

So, these 10uA seems to be a very worst case value, maybe for maximum operating temperatures...

And anyway, this 10uA bias current will only be transtaled as a +-50mV DC offset for the digitized waves. This value could be lowered by using smaller resistors, but I don't think this is worth of the extra current consumtion.

[charli va]

Hi my friends! Jesús when you said that LVDS+- should be flat, you are refering without connect the source signal? i dont' understand well, i'll search a typical LVDS+- signals images and appears an square waves or something like this, i think i don't understand what do you tell me.

I'm out of home an my "portatil lab" is not big and i haven't here passive components like ina shop XD, i only have a small capacitor(10pf) and a 10k resistor to try the fb RC filter,  i know is not the correct RC filter, but the  filter signal i think with the correct values could be a sine and its inverse, i'll try at the end of the week with the correct values (or could that i break something to obtaine this passive  components XD).

I think could not be very useful but i attache the fb signal and the bad filtered.

On the other hand, I am thinking that the Alhambra II board has a 200Ohm resistance in each GPIO and I have not taken it into account and although it is of very little value, it will be modifying our acquisition circuit.

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[Jesus Arias]

Hi, Charli

Pin #1, lvds-, has to be just an horizontal line at 1.65V. In your previous snaps it was a sine as big as the input signal, so, something was wrong. Open ground or something like that, maybe...?

And, when running properly, lvds+ is almost the same 1.65V horizontal line. You can get some sine there, but much smaller than the input. The feedback of the SD converter tries to keep that input at the same level than lvds- (like for opamps).

These 220ohm resistors don't play a significant role here because our resistors are much higher than that. They are mainly a protection for the FPGA pins.

Good luck and nice "bridge" ;) I'm going to be offline for some days...

[charli va]

Thanks for all Jesús! and enjoy the break!

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[Jesus Arias]

Just a reminder: Don't forget to connect the FPGA ground to our circuit ground. I didn't draw that connection on my previous schematic but it is really needed.

[charli va]

Yes! this is connected from the begining i need to review all the circuit, and look for the error. Thanks again!

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[vidal orellana]

Buenas tardes estimados.

Tengo una consulta con respecto a modulo de audio.

Puede ser posible integrar un sensor de vibraciones para sacarlo por este modulo de audio.

Muchas gracias por su tiempo.

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[Jo mo]

Hola Oswaldo,

I do not know what is your sensor and what you want to do with it (just trigger an event or measure precisely the vibrations)!

But In theory, if your vibration sensors outputs a voltage in the range 0 to 3.3V and is able to output some current to drive our ADC input, you can use this ADC.

if not you may need to insert a buffer/amplifier stage to adapt voltages and supply enough current to the ADC input.

Have a look at this page.

 buenas noces ;-)

[vidal orellana]

Gracias estimado.

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[charli va]

Hi my friends!! my LVDS ADC is alive!!! :)

Today, faced with this circuit worthy of x-file, I decided to start from scratch and redo the circuit, taking the opportunity to measure each stage and understand the theory.

And bang! In one of the 15K potentiometers the current did not pass or gave random values with peaks, I couldn't believe it... continuing with the circuit and placing the capacitor, it didn't give the appropriate values either. .. this time it was not the capacitor but the breadboard, an area, it makes a bad connection in a lot of points XD.

Changed potentiometer and new breadboard, everything worked perfectly at the first time!

Even though they have been hard days because of a silly mistake, along the way I have learned a lot, I managed to understand how LVDS works, I already understood why LVDS+ and - had to be flat and how the comparator works, as well as the feedback test,... .the initial filter of the input signal is totally necessary, without it many wrong frequencies sneak in and for Icestudio side, I am going to release a new version of the serial terminal that you are going to love, I have to finish polishing this week but we already have a new display format hexadecimal in tests, dumped in a file, 8 and 16 bit process (easily expandable to 32 to see if anyone is encouraged) and some very robust serial communication blocks at 3Mbps (better than the original ones that we were using that were not stable on all computers).

The truth is that this thread is being exciting and very fruitful, thank you very much to all the participants :)

The next few days I am going to focus on closing these new ICestudio functionalities and some more things that I had almost finished (the global variables, ifdefs...) ...I want to finish these functionalities to create these new components in a generic way.

As soon as I finish these things I will do some tests with musical audio.

Joaquim, the ADC has done nothing more than open a very interesting line to work with sound, count on me for whatever comes.

For those curious about how the result was (yellow is source signal, pure tone at 641Hz,and 1.6V peak to peak) :

1) LVDS -, totally flat:

2) LVDS+, flat with a very little noise:

3) Feedback, as "random" signal:

4) The record signal by sigma delta in the fpga , sended at 3Mbps to the pc (so beautiful!)

5) More beautiful, the FFT:

6) Attached the sound in wav, is courious but i think is an octave down te original, this makes me think there may be something wrong or something that needs to be adjusted, but as a starting point we have made a big leap

These days I will be preparing  Icestudio blocks and I will pass them on to anyone who wants to test them. I have to organize a few things first and encapsulate the verilog. Give me a couple of days for anyone who wants to test it. What do you think if we call it iceAnalog for the basic blocks (lvds input and output, adcs, sigma-delta blocks, dca...)?

Thank you very much again to the entire team, let's continue!

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