Verilog legible desde icestudio / Better verilog generator
Carlos Venegas
Hola a todos,abro un hilo nuevo. porque se nos van a hacer "super hilos" para comentaros esta nueva feature, Demócrito acaba de mandar un mensaje , os dejo enlace, enseñando como usar el nuevo visor de grafos.
Hasta ahora, el Verilog que genera Icestudio usaba nombres tipo v1a2b3 para todo: puertos, señales, instancias… Funcionaba, pero era imposible de seguir y eso tenía consecuencias, no solo para seguir el contenido en verilog, sino que lo hacía inusable para testbenches o para sacarle partida a los grafos.
Eso se acabó, pensaba sacar esto en siguientes fases pero como está llendo todo muy bien me lancé ayer a integrar el nuevo compilador que ya tenía hecho en la nueva versión del motro y Demócrito lo estuvo probando y parece que ha quedado bastante sólido por lo que os lo liberamos. El generador de código ha sido renovado a fondo:
Nombres con sentido en todo el diseño
- Puertos del top: llevan la etiqueta que pones al bloque, clk_v0b8ac4, led_v6a99a7 (el sufijo garantiza unicidad aunque repitas nombres).
- Puertos de los módulos internos: también legibles (Press_v64879c, pin_vd9601b).
- I/O sin etiquetar (muy común en bloques de colecciones): reciben nombres posicionales in0, in1, out0… en vez de un hash opaco.
- Instancias: cada bloque colocado se llama por su tipo, TFF_verilog_vd531e1, Button_tic_v868fc9 , así los scopes del VCD y las cajas de apio graph se identifican de un vistazo.
- Señales internas: nombradas por quién las genera — Button_tic_Press_w1, PushButton_w4, code_data_w0, adiós a los w0, w1, w2… anónimos.
- Módulos auto-documentados: cada módulo del Verilog exportado lleva delante el nombre y la descripción de su bloque.
El resultado: abres el VCD en GTKWave y las ondas se leen solas. El testbench generado conecta .led_v6a99a7(led) y declara reg clk; wire led;. El diagrama de apio graph por fin cuenta la historia de tu diseño.
Errores que se encuentran solos
Si un módulo enterrado a varios niveles de profundidad tiene un error, ahora el bloque que lo contiene aparece marcado con la admiración en el nivel superior, y al ir entrando el rastro te guía nivel a nivel hasta el bloque de código exacto, en rojo y con la línea anotada. El rastro se mantiene mientras navegas y se limpia en el siguiente verify/build. (De paso se arregló el resaltado de bloques genéricos, que llevaba tiempo roto).
Builds más estables y rápidos
El código generado es ahora determinista: el mismo diseño produce siempre exactamente el mismo Verilog, da igual en qué orden dibujaras los cables. Eso significa caché de compilación de apio más efectiva
(rebuilds más rápidos) y diffs limpios si versionas el Verilog exportado por ejemplo con git (esto es la bomba para diseños grandes).
Y varios bugs cazados por el camino
- Dos bloques con la misma etiqueta rompían el testbench generado.
- I/O sin nombre generaba reg 0; (Verilog inválido) en el testbench.
- Bloques guardados sin nombre de paquete producían Verilog incompilable.
Próximamente (si vamos viendo que todo va a buen ritmo):
- Alias por instancia: podrás poner nombre propio a cada bloque colocado (contador_principal en vez de AND2_v57aa83) y ese nombre fluirá a instancias y señales. El motor ya lo soporta; falta la interfaz (esto no está hecho en esta versión de icestudio y tengo que ver como meterlo para que sea cómodo y no sea una chapucilla).
Compatibilidad 100%: nada cambia en tus ficheros .ice , solo el código generado. Todos los diseños existentes siguen compilando exactamente igual.
ENGLISH
Hi everyone,
I’m opening a new thread because otherwise we’re going to end up with “super threads” for everything. I wanted to tell you about this new feature. Demócrito has just posted a message — I’ll leave the link here — showing how to use the new graph viewer.
The functionality already existed in Yosys, Apio added support for it by generating an SVG or PDF, and I have now integrated it into Icestudio with a viewer. But none of this would really make sense without the feature I’m announcing now, which has been requested for a very long time.
If any of you have ever tried to follow code generated by Icestudio, you will have seen — and suffered — that it was practically impossible. All signal names were random hashes, names changed on every build, the order changed, wires had generic names everywhere…
From now on, Icestudio generates readable Verilog, from end to end.
Until now, the Verilog generated by Icestudio used names like v1a2b3 for everything: ports, signals, instances… It worked, but it was impossible to follow. This had consequences not only when trying to understand the Verilog itself, but also when using it for testbenches or when trying to take advantage of graphs.
For example, in GTKWave you could not tell which signal was which. Many users told us that they prototyped in a text editor and only moved to Icestudio later because of this.
That is now over.
I was planning to release this in later phases, but since everything is going very well, yesterday I decided to integrate the new compiler, which I had already built for the new engine, into the current version. Demócrito tested it and it seems to be quite solid, so we are releasing it to you.
The code generator has been deeply renewed:
Meaningful names across the whole design
Top-level ports: they use the label you assign to the block, for example clk_v0b8ac4 or led_v6a99a7. The suffix guarantees uniqueness even if names are repeated.
Internal module ports: these are also readable, for example Press_v64879c or pin_vd9601b.
Unlabelled I/O, which is very common in collection blocks, now receives positional names such as in0, in1, out0… instead of opaque hashes.
Instances: each placed block is named after its type, for example TFF_verilog_vd531e1 or Button_tic_v868fc9. This makes VCD scopes and Apio graph boxes immediately recognizable.
Internal signals: named after what generates them, for example Button_tic_Press_w1, PushButton_w4, code_data_w0. Goodbye to anonymous w0, w1, w2…
Self-documenting modules: each exported Verilog module now includes the name and description of its block before the module itself.
The result: you open the VCD in GTKWave and the waveforms basically read themselves. The generated testbench connects .led_v6a99a7(led) and declares reg clk; wire led;. The Apio graph diagram finally tells the story of your design.
Errors that almost find themselves
If a module buried several levels deep contains an error, the block that contains it is now marked with an exclamation mark at the top level. As you enter each level, the trace guides you down until you reach the exact code block, highlighted in red with the relevant line annotated.
The trace remains while you navigate and is cleared on the next verify/build. As a side effect, the highlighting of generic blocks, which had been broken for some time, has also been fixed.
This has been half new feature, half bug fixing, because the old Icestudio did this only partially, sometimes correctly, sometimes not.
In the new version there is also an error list that lets you jump directly with one click, without navigating manually, just like in a code editor. But without the new engine, adding that cleanly is complicated unless we start patching things in a messy way. We’ll see. If not, we’ll have it fully integrated soon.
I’m only mentioning it because it is already done, so nobody spends time on it unnecessarily. The thing is that the new Icestudio is multi-view: you can have several blocks open at the same time, like in CAD tools.
I won’t tease you any further. Once we finish this phase, I’ll prepare a roadmap with everything that is already implemented in the new engine and what comes next.
More stable and faster builds
The generated code is now deterministic: the same design always produces exactly the same Verilog, regardless of the order in which you drew the wires.
That means Apio’s compilation cache becomes more effective, rebuilds are faster, and diffs are clean if you version the exported Verilog, for example with Git. This is huge for large designs.
And several bugs were caught along the way
Two blocks with the same label broke the generated testbench.
Unnamed I/O generated reg 0; in the testbench, which is invalid Verilog.
Blocks saved without a package name produced uncompilable Verilog.
Coming soon, assuming everything keeps moving at a good pace:
Instance aliases: you will be able to give each placed block its own name, for example main_counter instead of AND2_v57aa83, and that name will flow into instances and signals. The engine already supports this; what is missing is the interface. This is not included in this Icestudio version yet, and I still need to see how to add it in a way that feels comfortable and does not become a hack.
100% compatibility: nothing changes in your .ice files, only the generated code changes. All existing designs continue compiling exactly the same way.
I hope you keep enjoying it!
Jo mo
Carlos Venegas
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Regards,