SNES Controller Block for ICE40 and ECP5

[beni...@gmail.com]

Hello everybody, 

The project I proppose today is is the implementation of a SNES controller 

I got the instance from here :https://fpgalover.com/ip-cores/snes-controller-core
You can connect the Vcc of the controller to 3.3 volt for ECP5 ( in Alhambra board you can connect to 5 V because you have 5 V tolerant pins)

The connections are

With my Colorlight 5A-75F, the instance is only working with the r botton if I don't connect the rest of output LED blocks.

 When I connect more than r , there are not signals of CLK_SNES and LATCH, so the physical SNES controller doesn't receive these 2 signals and doesn't send the LATCH signal to the FPGA.

Maybe is a problem of a CASE statement in IceStudio, it is really strange 

Please, could anybody that use Alhambra test this project using your onboard 8 LEDs to test at least 8 actions of the controller ???? 

Regards

[Alexander Lang]

I will try it but I need a SNES controller first 😅

Cheers

Alex

--
Has recibido este mensaje porque estás suscrito al grupo "FPGAwars: explorando el lado libre" de Grupos de Google.
Para cancelar la suscripción a este grupo y dejar de recibir sus mensajes, envía un correo electrónico a fpga-wars-explorando-el...@googlegroups.com.
Para ver esta conversación en el sitio web, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/428424a4-5bfa-4f8d-9b92-6d8f89ead544n%40googlegroups.com.

[beni...@gmail.com]

Yes, You will need a SNES contoller

For people of alhambra, I don't remember if your LEDs use a positive or negative logic.

In case of using negative logic , you need to change the line 53 of the controller 
From 
buttons_snes[11:0] <= ~buttons_temp[11:0];    //  (This is for positive logic of your LEDs)
To
buttons_snes[11:0] <=  buttons_temp[11:0];     //  (This is for negative logic of your LEDs)

Regards

Fernando

[Jo mo]

Hello Fernando,

I convert your snes file to my colorlight i5 board (just changing pin assigment).

When I do a verify, I got 2 errors:

-          reg finish; cannot be driven by primitives or continuous assignment Verilog

-          reg idle; cannot be driven by primitives or continuous assignment verilog

 

I solved them by changing the reg type to wire at lines 34 and 35. I hope it does not break the function of the module.

For those like (me that) do not have a snes controller for testing. It should be possible to simulate it with a 16 bit shift-register module.

-          Clocking it with clk_snes

-          Enabling it with a long pulse (16 x 12 microsec). This one being triggered by the latch_snes pulse.

-          And using the last stage bit of the shift register as data-in to snes controller input

timing diagram of snes controller comunication

[beni...@gmail.com]

Hi Joaquim

The registers finish and idle can be commented or eliminated because they are not used.

You can test the module without SNES controller. Try to program the board and study the signals CLOCK and LATCH_SNES that they are generated inside the FPGA, if you have a logic analyzer you can test both signals.

In my case when I only connect the r_LED , it is working and the both signals are generated correwctly, but if I try to connect more LEDs , my logic analyzer doesn't detect any signal in LATCH and CLK pins

Do not run simulation because the simulation works perfectly. For me simulation was ok, but in real hardware is when the problems came.

Thanks and regards

Fernando

[Jo mo]

Hello Fernando,

Following your instruction, I could reproduce the problem.

An after playing an learning a bit  :-)

I replace the line 28

reg [11:0] buttons_snes=12'd0;

by

reg [11:0] buttons_snesz_zero=12'd0;

assign buttons_snes[11:0]= buttons_snesz_zero [11:0];//

And it seem ok now on my machine.

 

Of course, I could not test the full function without the physical controller.

[beni...@gmail.com]

Hello Joaquim,

if you replace the line by

reg [11:0] buttons_snesz_zero=12'd0;

assign buttons_snes[11:0]= buttons_snesz_zero [11:0];//

In  the line 

always@(posedge pre_finish)

begin

buttons_snes[11:0]<=buttons_temp[11:0];

end

Icestudio gives you an error because you can not assign and letter inside of always give other value

So, I don't understand the changes

If a put a intermediate variable buttons_snesz_zero,  I got the same result and the same problem

Regards

Fernando

[Jo mo]

if you want to try with my modded file

here it is

[beni...@gmail.com]

Joaquim,

Your code gives an error. I cannot build the bit file with your ice file.

You cannot assign the variable button_snes  and later using the same variable in the line 52. So the variable buttons_snes_zero is not doing anything.

Likewise, you have to comment the line 43  or uncomment the line 32

Regards

Fernando

[Jo mo]

ah yes, you are right,

if i hit verify, i have the same error.

but it work with my file when im just buiding and uploading. ??

i have to dig a quite bit more in verilog manuals. Specially for understanding those reg, wire, assign subtilities :-)