A Processor I Have Designed

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Suminda Sirinath Salpitikorala Dharmasena

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Oct 12, 2006, 1:52:54 AM10/12/06
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Dear Sir,

I am post graduate student in reading for a master's degree in Industrial Mathematics and have a keen interest in computer architecture. My undergraduate is a B.Sc. in Computing and Information Systems. I am presently employed as a quantitative analyst in an offshore investment research firm. However I continue to find time to carry out my independent research in to the computing field. I have over the years developed an invention for a micro processor which I want to commercialize. I hope to use the funds from this project for my PhD studies and more advanced research in the field of computing.   

The design I have made is as follows;

The Instruction Set Architecture (ISA) used in this computer architecture runs instructions in a highly parallel way. These processors have loosely coupled functional units (FUs). These FUs have registers hardwired to them. Useful computation is achieved by moving the registers from one to another. This way data can be pushed through a series of FUs which transforms it. When many such moves are made in parallel, it facilitates the execution of many instructions. Further details of this can be found in the attached paper. In a nutshell, this design would speed up the computation by making instructions as parallel as possible. Furthermore this does not have a decode phase. This is achieved by making the instruction to be arranged in a multiple recurring manner, so that the instruction is implied by its position, eliminating the need of using an op code to identify the instructions

This processor would increase the execution speed of certain classes of algorithms like Neural Networks by many folds. More speed can be gained when the dependencies between instructions are lesser. Generally, some degree of performance improvement is expected. Therefore, this can be used in super computing and application specific computing. Also since this architecture is a simplification of current architecture, the development as well as testing would be easier, cheaper and less problematic.

I would much appreciate if further this invention so it becomes a commercial reality.

Thanks in advance.
Regards Suminda.

--
Thanking you.
Best regards,
Suminda Sirinath Salpitikorala Dharmasena B.Sc. (Hon.) Comp. & I.S., Lon.

The intuitive mind is a sacred gift and the rational mind is a faithful servant. We have created a society that honours the servant and has forgotten the gift. - Albert Einstein

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IISC - 20060910224119 - Suminda Sirinath Salpitikorala Dharmasena.pdf
IISC-DISC-SISC-RMISC - 20060924082324 - Suminda Sirinath Salpitikorala Dharmasena.pdf
c__PCT-SAFE_Temp_00000001_SET__receipt.pdf
Brief Paper IISC v2 - 20060924081509 - Suminda Sirinath Salpitikorala Dharmasena.pdf

Gayal

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Oct 12, 2006, 10:24:35 AM10/12/06
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I am impressed with your Design.
How much cost do you estimate to build a working prototype?

Your references and bibliography in the paper is ambiguous

--
Gayal Rupasinghe
SU-APIIT
"The willingness to make a commitment even when results are unknown."

Mifan Careem

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Oct 13, 2006, 1:18:05 AM10/13/06
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Hi Suminda,

Impressive. But I'm not too sure whether you intended to post the documents and details to this address, as this is a group mailing list, for FOSS based discussions in Sril Lanka. Furthermore, there are no 'sir's' here :)

Just thought you should know.

Regards

Mifan
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