Download Intel Easy Clean Me

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Fortun Bawa

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Jan 9, 2024, 8:39:49 AM1/9/24

to flugalride

We noticed, in dual-socket setup with *"directory mode" disabled*, some write-backs to DRAM of clean cache lines (i.e. that were only read and never modified by anyone). This "issue" is very present in case all the HW prefetchers are enabled and very rare but still present when they are all disabled.

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In general terms, it does not make any difference whether such a clean eviction is dropped or written back to DRAM, but it is certainly possible that some detail of the implementation of the snoop filters or L3 or memory directories makes writing the line all the way back to memory the preferred option.

It is also possible that this occurs for some types of eviction operations and not for others. For example, clean lines evicted from the L2 due to Snoop Filter Evictions may behave differently than clean lines evicted from the L2 due to loads into the L2.

The processor family has the unusual characteristic that the associativity of the victim cache (11-way L3) is lower than the associativity of the Snoop Filter (12-way) or the L2 caches (16-way). This can lead to pathological conflict behavior (e.g., -paper-hpl-and-dgemm-performance-variability-on-intel-xeon-platinum-8160-processors/), which could easily result in unexpected cache transactions (either as a deliberate performance mitigation, or as the unexpected occurrence of a "corner case" transaction that exists for obscure reasons known only to the design team).

"In general terms, it does not make any difference whether such a clean eviction is dropped or written back to DRAM" => I agree with you that it is harmless for the system coherence, but not for us where our in-DRAM processors changed its content and got overwritten by those clean write-backs

My guess that this is an L2->L3 victim that the L3 did not accept was just a guess -- it has the right semantics and I have worked on processor designs that allowed for a cache to ignore a transaction (and let it pass through to the next level) if the cache was "too busy". For the case of clean data, dropping the WB would be "coherent", but that also requires a decision, and it could have been easier to just let the data bypass.

The core performance counter event IDI_MISC.WB_DOWNGRADE counts the "number of lines that are dropped and not written back to the L3 as they are deemed less likely to be reused shortly". My inference here is that no data WB is generated by the L2, but that there would still be a "Clean Eviction Notice" sent to the Snoop Filter. This strongly suggests that the L2 has a role in the decision to send clean victims to the L3, but that does not mean that the L3 cannot also have a role.

For ECC-enabled systems, the DRAM "scrubber" may also rewrite clean lines. On SKX, the uncore guide notes that the IMC_WRITES event does not count writes due to ECC errors. The IMC has a counter for correctable errors, but I have never tried to test it. (We immediately service systems that throw more than a few correctable errors per day, so there is little incentive to study these errors in more detail.)

And what puzzles me most is that the problem arrives only in dual socket, I can't reproduce those clean write backs in a single socket configuration: I may be completely wrong (and at this point I have not been able to prove my point) but this seems like directory mode is still partially enabled (remember that I disabled it) and then some cache lines trigger a clean WB in order to update ECC bits that hold cache line state.

I finally (better late than never...) found a way to measure those clean write-backs. Our DRAM architecture is a bit special: BG0 and BG1 have DRAM whereas BG2 and BG3 don't. I observed the clean writebacks on BG0 and BG1 with our in-DRAM processors in a test that only reads to BG0 and BG1 but that writes to BG2.

A different approach that might get lucky would be to look in the Intel patent portfolio for a phrase that maps to "d---- b----- p-----". Pretty easy regex on plain text -- not sure how to do in on a PDF or HTML source....

The ME is cleaned properly and the image looks just fine. Why did you want the ME region cleaned in the first place? After the new SPI image is flashed with cleaned ME region, remove power from the laptop (cord + battery), press the power button a few times (nothing visible should happen) and leave it for 1 minute. Then plug the battery and cord again and try again.

HI. can anybody clear this asus X554L bios for me.

i found this bios from web but this is not clear.

this bios secure boot function is disabled, so if enabled it no display.

and display comes after 45 sec late.

i already try to clean the me but never couldnot success.

when flash my working bios and try to greset with fpt it also not success. but given me this following error.

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Before I upgraded to the new M1 machine, I was having a lot of speed issues with my previous Intel Macbook Pro. A month before giving up and buying a new M1 MacbookAir, I suspected that the macOS installation and apps/tools I installed over many years were perhaps the sources of the speed issues. I backed everything up and planned a clean re-install on the Intel Macbook Pro. End result is not seeing the speed lift I expected and finally giving in to buy a new M1 Macbook Air which has been amazing as far as the speed I wanted from my computer.

Before installing any new app. This is actually a great opportunity to re-evaluate your relationship with all the tools/apps you use daily basis. Breaking digital habits is hard. Especially if you have everything set up already. But clean install is probably the best time to re-evaluate how much value each app is bringing to your day-to-day and the cost of using system resources on your computer. I have asked the same question and tentatively came up with the following list to use alternatives of the apps/tools I was using. A surprising amount of them had open-source alternatives so I could support the open source community as well as not need to pay or worry about proprietary licenses of the apps I was using.

Making sure you backup all of your .env files while you take backup of your old mac. This is probably the most important when you need to restore your local development environment. Documenting and pulling your code from the CVS is the easy part. You will need to re-create from scratch or use the .env files you backed up. Constructing the right credentials again would take extra effort if you are not organizing your credentials in tools like 1password.

I hope these would give you a good reference point if you are considering doing a full/clean install or bought a new mac and looking for ways to quickly set things up. I also have most of these documented that I refer to them occasionally.

I migrated with a time machine backup on a hard drive. No problems, but I made sure to clean up the old computer really good before I did the migration. I still have the impression that I have a little bit of bloating going on, but nothing serious.

I've done migrations using Time Machine and with a new clean install. When I setup my M1 Mac Mini I decided to go with a new install because I figured that I didn't want to copy over all the builds and stuff I had for Intel based machines. I have almost all of my account information and configurations synced to iCloud anyway. The clean install was really smooth and I ended up with much less wasted space and cleanup than I would have from using the Time Machine/Migration Assistant path.

NeonSilicon said:

Yours is a good reason to do a clean install. For the average (non-developer) user, these things are really no longer that much of a concern. For the sake of simplicity, I'd still recommend the Time Machine backup/Migration Assistant route.