4.6.7 VID Video Freeze Enable State
9.2 VoSPI Channel
The Lepton VoSPI protocol allows efficient and verifiable transfer of video over a SPI channel. The protocol is packet-based with no embedded timing signals and no requirement for flow control. The host (master) initiates all transactions and controls the clock speed. Data can be pulled from the Lepton (the slave) at a flexible rate. This flexibility is depicted in Figure 14, which shows the use of a relatively slow clock utilizing most of the available frame period as well as the use of a fast clock that bursts frame data. Once all data for a given frame is read, the master has the option to stop the clock and/or deassert the chip select until the next available frame. Alternatively, the master can simply leave the clock and chip select enabled, in which case Lepton transmits discard packets until the next valid video data is available.
The basic process for establishing synchronization is listed below:
Deassert /CS and idle SCK for at least 5 frame periods (>185 msec). This step ensures a timeout of the VoSPI interface, which puts the Lepton in the proper state to establish (or re-establish) synchronization.
Assert /CS and enable SCLK. This action causes the Lepton to start transmission of a first packet.
Examine the ID field of the packet, identifying a discard packet. Read out the entire packet.
Continue reading packets. When a new frame is available (should be less than 39 msec after asserting /CS and reading the first packet), the first video packet will be transmitted. The master and slave are now synchronized.