USRP immediate error when signal exists

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Ofir

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Sep 26, 2013, 12:52:19 PM9/26/13
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Hi there!

I run "sudo runcf ./osld_rx_usrp.app ./config".
When there is no tx signal (either because the other PC is not running TX, or because I took the antenna off) everything is "running". When I run uhd_fft I see the signal load and clear. Without antenna it is -70 dbm which is at least 20 dbm above noise; with antenna it is -20 to -30 dbm. When there is a signal I immediately get:

"""
Module resdemapp_pdcch returned error from work() function. Trying a clean stop
Total blocks: 1 Total errors: 1 BLER=1
Total blocks: 0 Total errors: 0 BLER=-nan
Total blocks: 0 Total errors: 0 BLER=-nan
Waveform ./osld_rx_usrp.app was cleanly removed from the system.
"""

I added some debug prints to your code and got (innermost error first):
"""
>> Error in line: /home/ofir/dev/aloe/modrep_osld/lte_lib/grid/pcfich.c:20
Error allocating PCFICH: REG (18,0) not found (i = 1) #######I added the i = %d
Error in line: /home/ofir/dev/aloe/modrep_osld/lte_lib/grid/base.c:363

Error initiating channel PCFICH
Error in line: /home/ofir/dev/aloe/modrep_osld/lte_lib/grid/base.c:394

Error in line: /home/ofir/dev/aloe/modrep_osld/lte_resource_demapper/src/dechannelize.c:203

i = 0; pdcch[i] = 1; nof_channels = 0

Error in line: /home/ofir/dev/aloe/modrep_osld/lte_resource_demapper/src/lte_resource_demapper.c:140

Module resdemapp_pdcch returned error from work() function. Trying a clean stop
Total blocks: 1 Total errors: 1 BLER=1
Total blocks: 0 Total errors: 0 BLER=-nan
Total blocks: 0 Total errors: 0 BLER=-nan
Waveform ./osld_rx_usrp.app was cleanly removed from the system.
"""

which means that "lte_reg_get_k(k,0,config)" returned NULL for "config->control.pcfich[i] = lte_reg_get_k(k,0,config);" when i==1, which means nothing to me.....


And another thing:
I think the reason I previously got BLER=1 multiple times is because the clock on one of my USRP is very inaccurate. I athink so because of "kalibrate" results (this app looks for GSM channels on air and tells you how off your USRP clock is). I am trying to fix this using clock synchronization between the 2 USRP's with their MIMO cable, I couldn;t test my theory because I keep getting the above errors,,

And yet another thing: to eliminate the real time factor I generated an .app file the records samples from usrp and put it into my own output.bin. Then I changed time_slot_ns=10000000; in config file and  ran osld_rx_file.app and see whats going on. I still get the same BLER=1 over and over (those samples were taken on a day when I didn't got kicked out by Module resdemapp_pdcch returned error from work() .

Thanks for all the great work you are doing!!

Ofir



Ismael Gomez

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Sep 26, 2013, 1:20:50 PM9/26/13
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Hi Ofir, 

The error seems to be that the resource mapper (receiver) can't decode the control channels correctly. Probably because the control format information field (CFI) has been decoded incorrectly. This is probably due to a bad synchronization. Were you able to find the PSS peak sequence every 5 slots? you should see in the PSS module's log that the peak is found every 5 slots **always**. Also, in the same file, check that the CFO is stable and that the sample where the peak is found is also constant in time. 

If all these is correct, you can try to force the CFI decoding editing the source file modrep_osld/lte_cfi_decoding/src/lte_cfi_decoding.c, Line 89, replace index++ by index=1;

Good luck,
Ismael  


2013/9/26 Ofir <ofir...@gmail.com>

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ra

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Feb 27, 2014, 5:34:52 PM2/27/14
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Hi Ismael,

I get the same error as the OP but I get it even when I tx/rx to/from file. When I make the change you mentioned, it doesn't quit but outputs BLER=1. I looked at the PSS log and I see sync every 5 time slots. Also SSS log had m1=0, m2=1. Any ideas where the problem might be?


Thanks.

Ra.

ra

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Feb 27, 2014, 5:36:41 PM2/27/14
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Quick followup: 

m0=0, m1=1, subframe=0
m0=1, m0=0, subframe=5
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