88e1512 Driver
Saundra Balock
At that point, I was able to modify the kernel's devices.c (arch/arm/mach-omap2/devices.c) to change the phy_id of cpsw_slaves[] from 0:00 to 0:13. After this change, CPSW could find the phy, however the id it gives is incorrect:
From the modification to the marvell driver I made, the id should be 0x01410dd0, not 0x4820482. If I modify the driver to change the id to 0x4820482, davinci_mdio.c will correctly find the driver for the phy. Even though it finds the driver, it does not actually work.
Hi Mikael,
I just noticed your question properly. First SerDes clocks are different from peripheral clock(which is the cpsw_iclk or emac_iclk). cpsw_iclk is derived from sysclk5 which in turn from sysclk4, which is from L3_PLL settings. Please check you L3_PLL registers to cross-confirm, what is being configured. MDC as you rightly pointed out, derives from this clock. You can adjust the divisor and check the MDC value. You can make it to 1MHz as expected and check if it is making any difference. AFAI read, there is only maximum limitation in MDC clock which 2.5MHz from the DM38x end and 25MHz from the marvel. Irrespective of the RGMII/MII/MGII configuration, if MDIO/MDC is proper, then you will be getting proper PHY ID
This driver enables the usage of an external Marvell PHY 88E1512 whichshould be connected to a SOC internal MAC controller. In a first step itis only the framework of the driver. Functionality will follow with asecond patch.
The following sections detail the modifications at the schematic level required to migrate from an 88E1512 device to the ADIN1300 device. Including a description of differences corresponding to each functional group of pins and differences in the hardware pin configuration of the device. A side-by-side pinout and package comparison and a feature comparison table are included for easy reference.
The ADIN1300 requires a minimum of 2 power supply rails, where the VDDIO is connected to the same power supply voltage as the MAC or as the PHY analog supply AVDD_3P3 (VDDA2P5). The 88E1512 can be powered with between 1 and 4 power supply rails depending on the configuration of using internal or external regulators. The VDDIO / VDDO supply rail powers the MAC interface and MDIO blocks, this can operate from 1.8V, 2.5V or 3.3V. The supply requirements are listed in Table 1 and Table 2.
Decoupling requirements for each device differ as described in Table 3. This table shows the decoupling for Analog, Digital and Core power supply pins for each device. For the different 88E1512 configurations and additional pins that require decoupling when the internal regulators are in use, see the datasheet.
The ADIN1300 includes power monitoring circuitry to monitor all of the supplies. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value.
The hardware strapping pins are read and updated at the de-assertion of reset for both devices. For the ADIN1300, the RESET_N pin resides in the AVDD_3P3 voltage domain. After 5 ms from the deassertion of RESET_N, the management interface registers are accessible and the device can be programmed.
In applications where the MAC interface is powered from VDDIO of 1.8V, level shifting of the RESET_N signal applied to the ADIN1300 may be required to ensure the voltage level on the RESET_N pin is in excess of the minimum input high threshold level.
The 88E1512 will be hardware configured after the de assertion of RESETn. The valid power to RESETn de-assertion time is 10mS. To reset the 88E1512 the RESET_N pin should be held low for a minimum of 10 ms.
A 25 MHz crystal or external clock source is used to provide the reference clock for both devices. A crystal can be connected to pins XTAL_I/XTAL_O (XI/XO), with both devices using the same external circuit. Or a 25 MHz refence clock can be provided on the input clock pin CLK_IN (XI).
The ADIN1300 has voltage mode line drivers with on-chip terminations so no external termination resistors are required. Both devices use voltage mode line drive for connection from the MDI_0:3_P/N (TD_P/M_A:D) pins to the magnetics and RJ-45 line using the same external circuit.
The ADIN1300 supports two LED pins, one on LED_0 and one on LINK_ST. The LED_0 has programmability of LED functions, with different blinking operation possible through MDIO configuration, the default mode is ON when Link is Up, blink if activity. The LINK_ST provides static information about Link up or down status.
For the LED_0 of the ADIN1300, it can be configured with 4-level strapping. The strapping configuration will have an impact on how the LED function operates and needs to be considered if the LED pins are used to directly drive an LED. If the strap pin is pulled high by the strapping resistors, (MODE_3/MODE_4) the output will be configured as an active low driver and conversely if the strapping input is pulled low (MODE_0/MODE_1), the output will be configured as active high. This LED circuit should be configured accordingly.
The ADIN1300 has a dedicated LINK_ST pin to provide information to the MAC on the status of the Link. By default, the LINK_ST pin goes high indicating the link is up and low to indicate the link is down. The LINK_ST polarity is programmable by setting the bit high GE_LNK_STAT_INV_EN.
The LINK_ST could be used to drive an LED, however it resides in the VDDIO voltage domain, therefore, when driving an LED in an integrated RJ45 jack where the PHY VDDIO is 1.8V, level shifting will be required. This can be done using a FET.
The ADIN1300 supports RGMII, MII and RMII MAC interface modes. The Marvell 88E1512 supports RGMII and SGMII. The following sections describe the RGMII interface for both devices and the MII and RMII interfaces for the ADIN1300.
The RGMII interface is the communication path between the PHY and MAC devices. The RGMII interface has a low pin count interface supports 10M, 100M and Gigabit operation, with a total of 12 pins for data transmission, reception and to signal errors or collision. It is the most common interface for Gigabit applications and has the lowest latency. Table 5 shows a pin overview of both devices for the RGMII MAC interface mode.
The MII interface is the communication path between the PHY and MAC devices. The MII interface has a high pin count, with a total of 15 pins for data transmission, reception and to signal errors or collision. It is sometimes used in 100M applications as it has a lower latency than RGMII and is much lower than RMII. Table 6 shows a pin overview for the ADIN1300 for the MII MAC interface mode.
The ADIN1300 sub-system registers provide user with ability to reconfigure which pin the COL and CRS functions are provided on (option of redirecting to GP_CLK, LINK_ST or INT_N). This requires a register write over MDIO interface to reconfigure.
The ADIN1300 can optionally provide a number of clock signals on the GP_CLK pin. This is configured via MDIO writes and the clocks available are a 125 MHz free running clock, 25 MHz clock and 25 MHz/125 MHz recovered clock.
When configuring any strapping configurations, ensure to review the default state of the MAC side, whether the pins are being driven when coming out of reset or if there are internal pulls. Understanding the behavior on the MAC side is key to ensuring there are no conflicts with the hardware strapping implemented, or to adjust the strapping resistor values if required.
The ADIN1300 uses a mix of 2-level and 4-level strapping options. In general, strapping pins are multi-functional and have different operation after the device is brought out of reset. The ADIN1300 has internal pull downs on many of its strapping pins (not all), therefore it would be possible to minimize external strapping resistors.
For the ADIN1300, speed configuration is done using two pins, PHY_CFG0 and PHY_CFG1. These pins do not have any internal pull resistors, therefore external strapping is required. Both pins support 4-level strapping, providing much flexibility in terms of the possible combinations, such as Auto-neg speeds shown in Table 9 or Forced modes shown in Table 10. Review the datasheet hardware configuration pin section for full detail on the possible settings using these pins.
The ADIN1300 uses two hardware pins, MACIF_SEL0 and MACIF_SEL1 to provide user ability to select different MAC interfaces. These two pins have internal weak pull downs, therefore the default operation would be RGMII with delays as shown in Table 12. To configure any other MAC interface mode, use 10kΩ pull up or pull down resistors to select accordingly.
The ADIN1300 uses two-level strapping for the four PHY address pins, either pull high or low to configure the PHY address, with an option of 16 unique addresses possible. Two level strapping provides a very robust PHY addressing scheme.
The ADIN1300 is available in a 40 lead LFCSP (6 mm x 6 mm footprint). The 88E1512 is available in a 56 Pin QFN (8 mm x 8 mm). Due to the smaller package footprint and differing pinout, the ADIN1300 is not a drop-in replacement for the 88E1512 product. It will require a re-spin of schematic and board layout to achieve this exchange.
The underside of the LFCSP package for the ADIN1300 includes an exposed paddle which should be soldered directly to the board with an array of vias for thermal purposes. There are also two exposed stripes adjacent to the exposed paddle. These are not intended to and do not need to be soldered to the board, they should be treated as a keep out area as they are connected to supply rails in the device, therefore should not be tied to ground and there should be no routing or traces on the PCB layer directly underneath them.
Both devices include integrated termination resistors on the MDI paths. These are voltage mode PHYs, no external resistors are required for biasing and no supply voltage is required at the center tap of the transformer.
Both devices can be hardware strapped to be used in an unmanaged configuration. Alternatively, they can provide access over the MDIO interface. Both devices support both Clause 22 and Clause 45 register access using both the 802.3 Clause 22 and Clause 45 management frame structures.
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