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port assignment in vhdl
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İhsan Koçak
Dec 31, 2011, 6:48:44 AM12/31/11
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hi all, i am new to vhdl, so this question can be easy for you.my
question is:how can i assign a value to an in port?
my port declaration is:
DATA_I : in std_logic_vector(7 downto 0);
when i try to assign a value to this port, modelsim says that a port
can not be driven.do you have any ideas about how to assign value to
an in port for debugging?
question is:how can i assign a value to an in port?
my port declaration is:
DATA_I : in std_logic_vector(7 downto 0);
when i try to assign a value to this port, modelsim says that a port
can not be driven.do you have any ideas about how to assign value to
an in port for debugging?
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