Confusion about FASED runtime configs/plus args

[Zixian Cai]

Hi all,

This is partly a question and partly documentation from my code spelunking.

So I have been religiously add "ddr3-FRFCFS-16G-4R-2133-OP.conf" to the custom_runtime_config of my config_hwdb.yaml. However, it just occurred to me that this might not do anything.

https://github.com/firesim/firesim/tree/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/custom-runtime-configs

First, I'm not sure what the state of runtime config generation is. It was removed in PR #1422 but added back in PR #1425.

During build time (make's replace-rtl target) however, I can notice content such as

+mm_relaxFunctionalModel_0=0
+mm_openPagePolicy_0=1
+mm_backendLatency_0=2
+mm_schedulerWindowSize_0=8
+mm_transactionQueueDepth_0=8
+mm_dramTimings_tAL_0=0
+mm_dramTimings_tCAS_0=14
+mm_dramTimings_tCMD_0=1
+mm_dramTimings_tCWD_0=10
+mm_dramTimings_tCCD_0=4
+mm_dramTimings_tFAW_0=25
+mm_dramTimings_tRAS_0=33
+mm_dramTimings_tREFI_0=7800
+mm_dramTimings_tRC_0=47
+mm_dramTimings_tRCD_0=14
+mm_dramTimings_tRFC_0=160
+mm_dramTimings_tRRD_0=8
+mm_dramTimings_tRP_0=14
+mm_dramTimings_tRTP_0=8
+mm_dramTimings_tRTRS_0=2
+mm_dramTimings_tWR_0=15
+mm_dramTimings_tWTR_0=8
+mm_rowAddr_offset_0=19
+mm_rowAddr_mask_0=32767
+mm_rankAddr_offset_0=16
+mm_rankAddr_mask_0=7
+mm_bankAddr_offset_0=13
+mm_bankAddr_mask_0=7

getting printed out.

This does match the logic in https://github.com/firesim/firesim/blob/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/midas/src/main/cc/bridges/fased_memory_timing_model.cc#L65 where each plusarg must have an index suffix

This comment, however, confuses me because it seems to suggest that all timing parameters must be explicitly specified as plusargs.

https://github.com/firesim/firesim/blob/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/midas/src/main/cc/bridges/fased_memory_timing_model.h#L172

But the actual C++ code only complains in the case where some but all timing parameters are overridden by plusargs.

https://github.com/firesim/firesim/blob/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/midas/src/main/cc/bridges/fased_memory_timing_model.cc#L169

So my conclusion is that the default configuration files (such as ddr3-FRFCFS-16G-4R-2133-OP.conf) provided in the repo is not useful anymore, because the plusargs don't have index suffixes, they will be ignored by the C++ part of the FASED bridge.

The actual default parameters are governed by code such as https://github.com/firesim/firesim/blob/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/midas/src/main/scala/midas/models/dram/DramCommon.scala#L66 where the JSON files under https://github.com/firesim/firesim/tree/b473147af03edc854a5bc2a95d1bc404c8711b2a/sim/midas/src/main/resources/midas/models/dram are read.

Is this understanding correct? Is runtime configuration generator cli still useful, and if so, how can I use it?

Also I wonder whether the register setting logic can prevent setting invalid value? For example, if maxRanks is set to 2 in Scala, and a rankAddr_mask=3 is set in a plusarg.

Many thanks!