FASED FR-FCFS Model Write Batching

[Connor Sullivan]

We are currently working on enhancing the FR-FCFS timing model. Work we are doing at the interconnect level (bandwidth regulation for real-time application domain) is suffering from the lack of write batching in the current version of FASED. The goal is to implement separate read and write transaction queues with high-low watermarking, write batching and write-to-read forwarding. We are mainly interested in amortizing the write to read bus turnaround timing constraint.

I have a baseline implementation, however, I have run into a problem that I can't solve. It seems that the FASED model is only accepting one write request at a time. More specifically, the write queue I have implemented only receives one write and then eventually the simulation goes into an infinite loop of refreshing the DRAM. It seems that the d$ and rockect-chip llc never issue another write back after the one reaches DRAM. I am using BOOM v3 as the core in the simulation.

Is there a limitation somewhere in the rocket-chip RTL that is leading to this? I don't think it has to do with my implementation as there aren't any indications of back pressure.

Any advice would be appreciated!

[David Biancolin]

Instead of replying all, i replied to author so i'm reposting. 

You are immediately returning the b-channel acknowledgement upon receipt of the AW and W requests right?

[Connor Sullivan]

I noticed that this isn't happening and am fixing it now. Thanks for the response David!