Firesim Synthesis Get Full Timing Report

[Karl Hallsby]

How can we get full timing reports from Vivado's physical synthesis process? I have some paths coming from a shared pipelined functional unit to a register that is failing timing and am trying to narrow down the problem. There is a report from the "Critical Path Optimization" phase that hints at the paths that fail to meet timing, but nothing more informative (example below).

2025-02-07 06:07:30,178 [flush       ] [INFO ]  [vivado] out: INFO: [Physopt 32-953] Path group WNS did not improve. Path group: uart_clock,clock_1000.0MHz,harnessbinder_clock,reference. Processed net: partition_wrapper/partition/firesim_top/top/sim/target/FireSim_/chiptop0/system/tile_prci_domain/element_reset_domain_rockettile/rocc_alu/identity_reg_n_0_[43].

I am familiar with how to do it with a normal Vivado flow (place -timing_summary somewhere), but don't know how to pass this kind of request to Vivado through Firesim's tooling.