AWS FPGA F1 DRAM Latency

[Rafael Ulises Luzius Pizarro Solar]

Hello guys,

Firesim guarantees cycle accuracy simulation in a context where an actual FPGA DRAM takes multiple FPGA cycles.

Did you measure the latency between the AXI request departing from the module that abstracts DRAM and the data arriving (~pure AXI realm)?

Best,

Rafael

[David Biancolin]

Hey Rafael,

As you might expect, that's a moving target that depends on the relative speed of the clock domains, and the load on the memory system. But on F1, with a 90 MHz simulator clock, a ballpark figure is about 40 cycles.

- David

[Rafael Pizarro Solar]

Hello David,

Thank you for your response.

This ballpark figure is from the memory request coming out of the L2 cache to the data coming back or from the request going out AXI domain ( -> DDR controllers) and data coming back?

- Rafael

[David Biancolin]

I'm talking just about the latencies in the FPGA memory system.

The latencies seen by the L2 is configurable and deterministic. That depends on what FASED model you select, and what diplomatic widgets you have between the L2 and the AXI4Port coming off your SoC. 

There's a workload we provide under deploy/workloads called ccbench that will measure these latencies for you for your design. I'd encourage you to run that. 

- David 

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[David Biancolin]

Just to clarify further, your simulation will not observe the 40 cycle figure i mentioned. For example, if you choose a Latency-Bandwidth Pipe your target (the simulated design) will deterministically observe the latency you requested -- which can range from 1 cycle to many thousands of cycles. This paper describes how that works in detail: https://people.eecs.berkeley.edu/~biancolin/papers/fased-fpga19.pdf