Register Address Generation in Generated Header.

[Muhammad Ali Akhtar]

In the latest firesim releases (1.20), for On-Premesis U280 / U250 FPGAs, in the generated headers, the addresses generated for MMIO registers are incremented by 4. e.g.

for master widget:

.INIT_DONE = 544,
.PRESENCE_READ = 548,
.PRESENCE_WRITE = 552,

and for  PEEKPOKEBRIDGEMODULE_struct{

     .STEP = 460,
     .DONE = 464,
      .PRECISE_PEEKABLE = 472

In the older firesim releases (like 1.10 or 1.11), the addresses generated for MMIO registers are incremented by 1. e.g.

 SIMULATIONMASTER_0_substruct->STEP = 128; 
 SIMULATIONMASTER_0_substruct->DONE = 129; 
 SIMULATIONMASTER_0_substruct->INIT_DONE = 130; 

Question: Why was address generation logic changed for newer firesim releases - which support On Prem (250/280) FPGAs? Is it a specific requirement of xdma IP for On Premesis FPGAs?

Basically, I am trying to add On-Prem FPGA support to older firesim release (1.10).

Muhammad Ali Akhtar