Possibility to implement xdma flow on Xilinx VCU190

[jin yuan]

Hi,

I would like to know if it is possible to implement xdma flow on Xilinx VCU190.

I have already checked the flow for vcu118. I found that it uses garnet to create hardware designs that communicate with a host system over PCI. But after I open the generated design, I find something weird. The XDMA ip for vcu118 provides the option for dfx over pcie. However, the xdma ip for vck190 doesn"t give this option. Since the given configuration of xdma selects dfx over pcie and it leads to the usage of the mcap_design_switch and cap interfaces, this makes me confused if I can do the same thing on vck190.

Best regards,

Jin

[Abraham Gonzalez]

You shouldn't need the DFX option given by Garnett for FireSim (you only need the AXI DMA, MMIO, and DDR interfaces - 512b/32b/512b respectively). As long as you have these interfaces into the simulator you should be fine.

--
You received this message because you are subscribed to the Google Groups "FireSim" group.
To unsubscribe from this group and stop receiving emails from it, send an email to firesim+u...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/firesim/10e9d176-5cc3-4453-a905-a20728e1af90n%40googlegroups.com.

--

Abraham J. Gonzalez

Electrical Engineering and Computer Science Ph.D. Student

The University of California at Berkeley

[jin yuan]

Hi Abraham,

I am wondering if the data width of axi interface must be 512b, is it possible to use a 128b data. And if the axi lite master interface is also required by firesim.

Best regard,

Jin

Abraham Gonzalez <abe.go...@berkeley.edu> 于 2023年9月13日周三 20:31写道：

You received this message because you are subscribed to a topic in the Google Groups "FireSim" group.
To unsubscribe from this topic, visit https://groups.google.com/d/topic/firesim/FHMGx31WWaM/unsubscribe.
To unsubscribe from this group and all its topics, send an email to firesim+u...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/firesim/CAH9JGgpvjknWSDvu5hAtQ6QnnPPHueZNOm-E0Zz_fKjTvMnzBw%40mail.gmail.com.

[Vincent “Starry starry night”]

Hi All,

I am also wondering if the interface must be 512b. Does anyone have a solution to this question? 

Thanks in advance.

--vincent

jin yuan 在 2023年9月28日 星期四下午6:43:30 [UTC+8] 的信中寫道：

[Abraham Gonzalez]

The AXI-4 Lite interface is required. All other interfaces are optional (assuming you set up the RTL configuration for the FPGA properly to not have the other interfaces).

As for the AXI DMA interface being 512b, I see no reason why this can't be changed, you should be able to make it more/less and then ensure that nowhere in the code 512b is hardcoded.

To view this discussion on the web visit https://groups.google.com/d/msgid/firesim/9d9808fb-2378-4373-9d2e-5f48c32796ffn%40googlegroups.com.

[jin yuan]

The firesim wrapper generated for my project has a axi dma datawidth of 512 bits. And the xdma ip I was using can only maximally generate axi traffic with data width of 128. Unfortunately, I didn't try to check the related firesim code to find solutions. Instead I just added a axi smart connect ip between xdma ip and firesim wrapper. This ip can do axi data width conversion.