SiFive Cache

[Connor Sullivan]

Hello,

Not sure if this would be more suited for the Chipyard group, but reaching out here. We are attempting to figure out the address mapping scheme that the last level SiFive cache uses. Specifically, we are trying to understand what bits of the address map to a specific bank in the cache.

Does anyone have any insight on this topic?

Best,

Connor Sullivan

[Jerry Zhao]

The cache lines are striped across the banks. Consecutive cache lines reside in separate banks. 

The BankBinder in rocket chip implements this. 

-Jerry

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[Connor Sullivan]

So it seems that the BankBinder is generating the bank structures, but we aren't seeing the address mapping scheme in this location. We had been looking lower down in the BankedStore of the SiFive as that's where we believed the address mapping was happening. We are interested in knowing how the address is decoded such that we can target specific banks of the l2 cache.

Thanks for your help!

[Jerry Zhao]

The BankBinder sets the "downstream" address ranges properly, so the Xbar or NoC can determine the routing table from the address ranges of all attached managers.

-Jerry

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[Connor Sullivan]

Hey Jerry,

Thanks for the pointer. I believe I was able to extract the information we were looking for. If you are able, could you confirm my understanding?

I extracted these address sets from BankBinder. Based on this and some simple tests, it seems that the 6th bit of the address is used to select the bank. Does this seem to be correct? This configuration is a 2 bank, 1MB, 8 way cache.

For reference, we are attempting to replicate the bank accesses that we had previously preformed on the Cortex-A57. I've attached an image from the reference manual. In this case the 6th bit of the physical address selects the bank. Is this similar to how a specific bank could be selected for the SiFive cache (of course depending on the configuration)?

Best,

Connor

[Jerry Zhao]

Memory is striped by cache line index, so the 6th bit (for every 2^6 = 64 bytes) is where the bank index starts, as you describe. This seems to match what you describe for the A57.

-Jerry

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[jin yuan]

HI Jerry,

The question I have is not relevant to this post. However this is the most recent post that I can find where member from firesim answers questions. Therefore, I post my quesition here.

Actually, I am trying to run the make command for the code under the directory firesim/platforms/xilinx_vcu118/garnet_firesim/cl_firesim. However, it seems there are some files missed, like  "$CL_DIR/design/FireSim-generated.defines.vh", "$CL_DIR/design/FireSim-generated.sv", and $CL_DIR/design/FireSim-generated.synthesis.xdc, and the design file for F1shim. Do you know where I can find these files.

Best,

Jin