DRC errors after changes in TracedInstruction module and TracerVmodules

[Manchem Chandana Sai Sri ee19b093]

Dear Sagar,

I've added an extra signal whose width is 210 bits to trace bundle, the compilation went fine but during the bitstream generation, drc check failed with the following error, Is it because the module is now of more width(data) than the normal TracedBundle?? But every cycle the width is not more than the default 512 bits(BridgeStreamConstants.streamWidthBits), then why is the expansion of RAMB depth is needed??

This is the error, any help would be greatly appreciated.

INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC CASC-29] CASCADE_ORDER: The RAMB36E2 cell partition_wrapper/partition/firesim_top/top/CPUManagedStreamEngine_0/TRACERVBRIDGEMODULE_0_to_cpu_stream_outgoingQueue/fq/ram_reg_bram_23 is cascaded in series to expand the RAMB depth. The cell has CASCADE_ORDER_B=LAST. The CASCADE_ORDER_B attribute is not set correctly. The first RAMB must have CASCADE_ORDER=FIRST, the last RAMB must have CASCADE_ORDER=LAST, and all other RAMBs in the chain must have CASCADE_ORDER=MIDDLE.
INFO: [Vivado_Tcl 4-198] DRC finished with 1 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.

Thanks

Chandana Manchem