Xilinx Dsp48e

[Ogier Dudley]

Ineed to make a implementation of a floating point division using System Generator and I my version of System Generator dont support the 'divider generator' so I was thinking several options to make the implementation. One is using the Xilinx DSP48 block.Does anyone knows if is posible to make a division implementation through a DSP48 xilinx block?Thank you for your help.

However, your best bet is to create a divider using 'coregen'. Launch 'coregen', create a new project and go to 'Math Functions -> Dividers' (the options appear depending on the target device). Then go through the wizard choosing your preferred setup.

Here's a bit more information on how to use 'coregen': 'coregen' will create a '.v' or'.vhd' instantiation file depending on the language you've chosen. It will run XST to generate a '.ncg' "blackbox" netlist so the implementation process can include it when you run 'ngdbuild'.

and you'll get the HDL instantiation and the netlist (and a bunch of other things in the process). Note that 'coregen' will generate its output where the input files are, not where it is invoked from, and there's no switch to indicate an output path!

The Xilinx DSP48 Macro offers a very easy interface, which abstracts the slice of Xilinx DSP48. It also simplifies the dynamic operation. This it achieves by making possible the multiple operations specification through some arithmetic expressions that are user defined. Furthermore, these specified operations can be enumerated, as well as chosen by a user through a single port present on your generated core.

Also, the DSP48 Macro helps in supporting a latency model whereby extra register stages are usually included so that all the input into the output paths features a similar latency. It backs three latency modes, which are expert, tiered, and automatic.

The tiered and automatic are the square types of latency models. Here, the difference is that the auto offers complete pipelines. The tiered on the other hand allows for finer control. Now, this could be very useful when making use of Xilinx DSP48 slices to serve as processing engines.

The Xilinx DSP48 block is known as the most complex of all the computational blocks available in the Xilinx FPGA. This block is known as an ALU (arithmetic logic unit), which is embedded in the FPGA fabric and is made up of three blocks which form a chain.

A good number of DSP designs work well with the architecture of the 7 series. In order to get the best benefit from using the architecture, you must understand the capabilities and features to ensure that the entry code of the design will take advantage of the resources. The resources of the DSP48E1 are automatically used for majority of the DSP functions as well as a good number of arithmetic functions.

Most of the time, the resources of the DSP ought to be inferred. Check out the documentation of the synthesis preferred for the guidelines so as to make sure of the right inference of DSP48E1 slice. The tool for synthesis helps in inferring the resources. The instantiation is useful in directly accessing the features of the Xilinx DSP48 slice. The recommendations for DSP48E1 use include:

The control of the multiplexers is achieved via dynamic control signals like CARRYINSEL, ALUMODE, and OPMODE. This enables great flexibility. Also, designs making use of dynamic opmodes and registers are more equipped to work with the capabilities of the xilinx DSP48 slice compared to the combinatorial multiplies.

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