Enhanced SpeedStep fix for newer VIA Eden CPU's

[Dimitry Andric]

Hi,

If you have one of the newer VIA Eden CPU's, you may get something like
the following in your dmesg:

cpu0: VIA Eden Processor 1000MHz ("CentaurHauls" 686-class) 1 GHz
..
cpu0: unknown Enhanced SpeedStep CPU, msr 0x04090a0904000a09
cpu0: using only highest and lowest power states
cpu0: Enhanced SpeedStep 1333 MHz (844 mV): speeds: 1333, 533 MHz

So the reported speeds do not correspond to the actual ones. This is
caused by incorrect detection of the FSB clock.

In such cases, please try the following diff, and send a dmesg of before
and after, plus "sysctl machdep.cpuid" output. Note, this may not fix
the "unknown" message, but it should start reporting the correct speeds.

Index: sys/arch/i386/i386/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.435
diff -u -p -r1.435 machdep.c
--- sys/arch/i386/i386/machdep.c 11 Jul 2008 03:03:07 -0000 1.435
+++ sys/arch/i386/i386/machdep.c 19 Jul 2008 00:52:52 -0000
@@ -1898,23 +1898,39 @@ void
cyrix3_get_bus_clock(struct cpu_info *ci)
{
u_int64_t msr;
- int bus;
+ int bus, model;

msr = rdmsr(MSR_EBL_CR_POWERON);
bus = (msr >> 18) & 0x3;
- switch (bus) {
- case 0:
- bus_clock = BUS100;
- break;
- case 1:
- bus_clock = BUS133;
- break;
- case 2:
- bus_clock = BUS200;
- break;
- case 3:
- bus_clock = BUS166;
- break;
+ model = (ci->ci_signature >> 4) & 15;
+ if (model == 0xd) {
+ /* VIA Eden Processor 1x00MHz ("CentaurHauls" 686-class) */
+ switch (bus) {
+ case 1:
+ bus_clock = BUS100;
+ break;
+ default:
+ printf("%s: unknown VIA (sig 0x%x) EBL_CR_POWERON "
+ "value %d (0x%llx)\n", ci->ci_dev.dv_xname,
+ ci->ci_signature, bus, msr);
+ break;
+ }
+ } else {
+ /* Other VIA's, until there's more information */
+ switch (bus) {
+ case 0:
+ bus_clock = BUS100;
+ break;
+ case 1:
+ bus_clock = BUS133;
+ break;
+ case 2:
+ bus_clock = BUS200;
+ break;
+ default:
+ bus_clock = BUS166;
+ break;
+ }
}
}