[PATCH 0/3] pinctrl/broxton: enable platform device in the absent of ACPI enumeration

[Tan Jui Nee]

Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.

The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.

All these three patches have dependencies on each other.

Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's

Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system

arch/x86/Kconfig | 4 ++
arch/x86/include/asm/p2sb.h | 27 ++++++++
arch/x86/platform/intel/Makefile | 1 +
arch/x86/platform/intel/p2sb.c | 99 ++++++++++++++++++++++++++
drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 119 ++++++++++++++++++++++++++++++++
drivers/pinctrl/intel/pinctrl-broxton.c | 43 ++++++++----
7 files changed, 283 insertions(+), 13 deletions(-)
create mode 100644 arch/x86/include/asm/p2sb.h
create mode 100644 arch/x86/platform/intel/p2sb.c

--
1.9.1

[Tan Jui Nee]

This is to cater the need for non-ACPI system whereby

a platform device has to be created in order to bind

with the Apollo Lake Pinctrl GPIO platform driver.

Signed-off-by: Tan Jui Nee <jui.n...@intel.com>
---
drivers/pinctrl/intel/pinctrl-broxton.c | 43 ++++++++++++++++++++++++---------
1 file changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index 5979d38..59cb7a6 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -1,7 +1,7 @@
/*
* Intel Broxton SoC pinctrl/GPIO driver
*
- * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2015, 2016 Intel Corporation
* Author: Mika Westerberg <mika.we...@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -1003,29 +1003,46 @@ static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);

+static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
+ { "apl-pinctrl", (kernel_ulong_t)&apl_pinctrl_soc_data },
+ { "broxton-pinctrl", (kernel_ulong_t)&bxt_pinctrl_soc_data },
+ { },
+};
+
static int bxt_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
- const struct acpi_device_id *id;
struct acpi_device *adev;
int i;

adev = ACPI_COMPANION(&pdev->dev);
- if (!adev)
- return -ENODEV;
+ if (adev) {
+ const struct acpi_device_id *id;

- id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
- if (!id)
- return -ENODEV;
+ id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
+ if (!id)
+ return -ENODEV;

- soc_table = (const struct intel_pinctrl_soc_data **)id->driver_data;
+ soc_table = (const struct intel_pinctrl_soc_data **)
+ id->driver_data;

- for (i = 0; soc_table[i]; i++) {
- if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
- soc_data = soc_table[i];
- break;
+ for (i = 0; soc_table[i]; i++) {
+ if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
+ soc_data = soc_table[i];
+ break;
+ }
}
+ } else {
+ const struct platform_device_id *pid;
+
+ pid = platform_get_device_id(pdev);
+ if (!pid)
+ return -ENODEV;
+
+ soc_table = (const struct intel_pinctrl_soc_data **)
+ pid->driver_data;
+ soc_data = soc_table[pdev->id];
}

if (!soc_data)
@@ -1047,6 +1064,7 @@ static struct platform_driver bxt_pinctrl_driver = {
.acpi_match_table = bxt_pinctrl_acpi_match,
.pm = &bxt_pinctrl_pm_ops,
},
+ .id_table = bxt_pinctrl_platform_ids,
};

static int __init bxt_pinctrl_init(void)
@@ -1064,3 +1082,4 @@ module_exit(bxt_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.we...@linux.intel.com>");
MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:broxton-pinctrl");
--
1.9.1

[Tan Jui Nee]

From: Andy Shevchenko <andriy.s...@linux.intel.com>

There is already one and at least one more user coming which
require an access to Primary to Sideband bridge (P2SB) in order
to get IO or MMIO bar hidden by BIOS.
Create a driver to access P2SB for x86 devices.

Signed-off-by: Yong, Jonathan <jonath...@intel.com>
Signed-off-by: Andy Shevchenko <andriy.s...@linux.intel.com>
---
arch/x86/Kconfig | 4 ++
arch/x86/include/asm/p2sb.h | 27 +++++++++++
arch/x86/platform/intel/Makefile | 1 +
arch/x86/platform/intel/p2sb.c | 99 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 131 insertions(+)

create mode 100644 arch/x86/include/asm/p2sb.h
create mode 100644 arch/x86/platform/intel/p2sb.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2dc18605..b678380 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -606,6 +606,10 @@ config IOSF_MBI_DEBUG

If you don't require the option or are in doubt, say N.

+config P2SB
+ tristate
+ depends on PCI
+
config X86_RDC321X
bool "RDC R-321x SoC"
depends on X86_32
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 0000000..686e07b
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,27 @@
+/*
+ * Primary to Sideband bridge (P2SB) access support
+ */
+
+#ifndef P2SB_SYMS_H
+#define P2SB_SYMS_H
+
+#include <linux/ioport.h>
+#include <linux/pci.h>
+
+#if IS_ENABLED(CONFIG_P2SB)
+
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+ struct resource *res);
+
+#else /* CONFIG_P2SB is not set */
+
+static inline
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+ struct resource *res)
+{

+ return -ENODEV;
+}
+

+#endif /* CONFIG_P2SB */
+
+#endif /* P2SB_SYMS_H */
diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile
index b878032..dbf9f10 100644
--- a/arch/x86/platform/intel/Makefile
+++ b/arch/x86/platform/intel/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_P2SB) += p2sb.o
diff --git a/arch/x86/platform/intel/p2sb.c b/arch/x86/platform/intel/p2sb.c
new file mode 100644
index 0000000..8be47a4
--- /dev/null
+++ b/arch/x86/platform/intel/p2sb.c
@@ -0,0 +1,99 @@
+/*
+ * Primary to Sideband bridge (P2SB) driver
+ *
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * Authors: Andy Shevchenko <andriy.s...@linux.intel.com>
+ * Jonathan Yong <jonath...@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+
+#include <asm/p2sb.h>
+
+#define SBREG_BAR 0x10
+#define SBREG_HIDE 0xe1
+
+static DEFINE_SPINLOCK(p2sb_spinlock);
+
+/*
+ * p2sb_bar - Get Primary to Sideband bridge (P2SB) BAR
+ * @pdev: PCI device to get PCI bus to communicate with
+ * @devfn: PCI device and function to communicate with
+ * @res: resources to be filled in
+ *
+ * The BIOS prevents the P2SB device from being enumerated by the PCI
+ * subsystem, so we need to unhide and hide it back to lookup the P2SB BAR.
+ *
+ * Locking is handled by spinlock - cannot sleep.
+ *
+ * Return:
+ * 0 on success or appropriate errno value on error.
+ */
+int p2sb_bar(struct pci_dev *pdev, unsigned int devfn,
+ struct resource *res)
+{
+ u32 base_addr;
+ u64 base64_addr;
+ unsigned long flags;
+
+ if (!res)
+ return -EINVAL;
+
+ spin_lock(&p2sb_spinlock);
+
+ /* Unhide the P2SB device */
+ pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x00);
+
+ /* Check if device present */
+ pci_bus_read_config_dword(pdev->bus, devfn, 0, &base_addr);
+ if (base_addr == 0xffffffff || base_addr == 0x00000000) {
+ spin_unlock(&p2sb_spinlock);
+ dev_warn(&pdev->dev, "P2SB device access disabled by BIOS?\n");

+ return -ENODEV;
+ }
+

+ /* Get IO or MMIO BAR */
+ pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR, &base_addr);
+ if ((base_addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+ flags = IORESOURCE_IO;
+ base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK;
+ } else {
+ flags = IORESOURCE_MEM;
+ base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK;
+ if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ flags |= IORESOURCE_MEM_64;
+ pci_bus_read_config_dword(pdev->bus, devfn,
+ SBREG_BAR + 4, &base_addr);
+ base64_addr |= (u64)base_addr << 32;
+ }
+ }
+
+ /* Hide the P2SB device */
+ pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, 0x01);
+
+ spin_unlock(&p2sb_spinlock);
+
+ /* User provides prefilled resources */
+ res->start += (resource_size_t)base64_addr;
+ res->end += (resource_size_t)base64_addr;
+ res->flags = flags;
+
+ return 0;
+}
+EXPORT_SYMBOL(p2sb_bar);
+
+MODULE_LICENSE("GPL");
--
1.9.1

[Tan Jui Nee]

This driver uses the P2SB hide/unhide mechanism cooperatively
to pass the PCI BAR address to the gpio platform driver.

Signed-off-by: Tan Jui Nee <jui.n...@intel.com>
---

drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index eea61e3..54fed50 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -359,8 +359,9 @@ config MFD_INTEL_QUARK_I2C_GPIO

config LPC_ICH
tristate "Intel ICH LPC"
- depends on PCI
+ depends on X86 && PCI
select MFD_CORE
+ select P2SB
help
The LPC bridge function of the Intel ICH provides support for
many functional units. This driver provides needed support for
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index bd3aa45..c28ca26 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -68,6 +68,10 @@
#include <linux/mfd/core.h>
#include <linux/mfd/lpc_ich.h>
#include <linux/platform_data/itco_wdt.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/types.h>
+
+#include <asm/p2sb.h>

#define ACPIBASE 0x40
#define ACPIBASE_GPE_OFF 0x28
@@ -94,6 +98,19 @@
#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])

+/* Offset data for Apollo Lake GPIO communities */
+#define APL_GPIO_SOUTHWEST_OFFSET 0xc0
+#define APL_GPIO_NORTHWEST_OFFSET 0xc4
+#define APL_GPIO_NORTH_OFFSET 0xc5
+#define APL_GPIO_WEST_OFFSET 0xc7
+
+#define APL_GPIO_SOUTHWEST_END (43 * 0x8)
+#define APL_GPIO_NORTHWEST_END (77 * 0x8)
+#define APL_GPIO_NORTH_END (90 * 0x8)
+#define APL_GPIO_WEST_END (47 * 0x8)
+
+#define APL_GPIO_IRQ 14
+
struct lpc_ich_priv {
int chipset;

@@ -133,6 +150,39 @@ static struct resource gpio_ich_res[] = {
},
};

+static struct resource apl_gpio_io_res[][2] = {
+ {
+ {
+ .start = APL_GPIO_NORTH_OFFSET << 16,
+ .end = (APL_GPIO_NORTH_OFFSET << 16)
+ + APL_GPIO_NORTH_END,
+ },
+ },
+ {
+ {
+ .start = APL_GPIO_NORTHWEST_OFFSET << 16,
+ .end = (APL_GPIO_NORTHWEST_OFFSET << 16)
+ + APL_GPIO_NORTHWEST_END,
+ },
+ },
+ {
+ {
+ .start = APL_GPIO_WEST_OFFSET << 16,
+ .end = (APL_GPIO_WEST_OFFSET << 16)
+ + APL_GPIO_WEST_END,
+ },
+ },
+ {
+ {
+ .start = APL_GPIO_SOUTHWEST_OFFSET << 16,
+ .end = (APL_GPIO_SOUTHWEST_OFFSET << 16)
+ + APL_GPIO_SOUTHWEST_END,
+ },
+ },
+};
+
+static struct pinctrl_pin_desc apl_pinctrl_pdata;
+
static struct mfd_cell lpc_ich_wdt_cell = {
.name = "iTCO_wdt",
.num_resources = ARRAY_SIZE(wdt_ich_res),
@@ -147,6 +197,15 @@ static struct mfd_cell lpc_ich_gpio_cell = {
.ignore_resource_conflicts = true,
};

+static struct mfd_cell apl_gpio_devices = {
+ .name = "apl-pinctrl",
+ .num_resources = ARRAY_SIZE(apl_gpio_io_res),
+ .resources = apl_gpio_io_res[1],
+ .pdata_size = sizeof(apl_pinctrl_pdata),
+ .platform_data = &apl_pinctrl_pdata,
+ .ignore_resource_conflicts = true,
+};
+
/* chipset related info */
enum lpc_chipsets {
LPC_ICH = 0, /* ICH */
@@ -216,6 +275,7 @@ enum lpc_chipsets {
LPC_BRASWELL, /* Braswell SoC */
LPC_LEWISBURG, /* Lewisburg */
LPC_9S, /* 9 Series */
+ LPC_APL, /* Apollo Lake SoC */
};

static struct lpc_ich_info lpc_chipset_info[] = {
@@ -531,6 +591,10 @@ static struct lpc_ich_info lpc_chipset_info[] = {
.name = "9 Series",
.iTCO_version = 2,
},
+ [LPC_APL] = {
+ .name = "Apollo Lake SoC",
+ .iTCO_version = 5,
+ },
};

/*
@@ -679,6 +743,7 @@ static const struct pci_device_id lpc_ich_ids[] = {
{ PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
{ PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
{ PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
+ { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
{ PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
{ PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
@@ -1050,6 +1115,57 @@ wdt_done:
return ret;
}

+static int lpc_ich_misc(struct pci_dev *dev, enum lpc_chipsets chipset)
+{
+ unsigned int apl_p2sb = PCI_DEVFN(0x0d, 0);
+ unsigned int i;
+ int ret;
+
+ switch (chipset) {
+ case LPC_APL:
+ /*
+ * Apollo lake, has not 1, but 4 gpio controllers,
+ * handle it a bit differently.
+ */
+
+ for (i = 0; i < ARRAY_SIZE(apl_gpio_io_res); i++) {
+ struct resource *res = apl_gpio_io_res[i];
+
+ apl_gpio_devices.resources = res;
+
+ /* Fill MEM resource */
+ ret = p2sb_bar(dev, apl_p2sb, res++);
+ if (ret)
+ goto warn_continue;
+
+ /* Fill IRQ resource */
+ res->start = APL_GPIO_IRQ;
+ res->end = res->start;
+ res->flags = IORESOURCE_IRQ;
+
+ apl_pinctrl_pdata.name = kasprintf(GFP_KERNEL, "%u",
+ i + 1);
+ if (apl_pinctrl_pdata.name)
+ ret = mfd_add_devices(&dev->dev, i,
+ &apl_gpio_devices, 1, NULL, 0, NULL);
+ else
+ ret = -ENOMEM;
+
+warn_continue:
+ if (ret)
+ dev_warn(&dev->dev,
+ "Failed to add Apollo Lake GPIO %s: %d\n",
+ apl_pinctrl_pdata.name, ret);
+
+ kfree(apl_pinctrl_pdata.name);
+ }
+ break;
+ default:
+ return -ENODEV;
+ }
+ return 0;
+}
+
static int lpc_ich_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
@@ -1093,6 +1209,9 @@ static int lpc_ich_probe(struct pci_dev *dev,
cell_added = true;
}

+ if (!lpc_ich_misc(dev, priv->chipset))
+ cell_added = true;
+
/*
* We only care if at least one or none of the cells registered
* successfully.
--
1.9.1

[Tan, Jui Nee]

> -----Original Message-----
> From: lkp
> Sent: Monday, April 11, 2016 12:35 PM
> To: Tan, Jui Nee <jui.n...@intel.com>
> Cc: kbuil...@01.org; mika.we...@linux.intel.com;
> heikki....@linux.intel.com; andriy.s...@linux.intel.com;
> tg...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> pty...@xes-inc.com; lee....@linaro.org; linux...@vger.kernel.org;
> linux-...@vger.kernel.org; Tan, Jui Nee <jui.n...@intel.com>; Yong,
> Jonathan <jonath...@intel.com>; Yu, Ong Hock
> <ong.h...@intel.com>; Voon, Weifeng <weifen...@intel.com>; Wan
> Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zain...@intel.com>
> Subject: Re: [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO
> pinctrl in non-ACPI system
>
> Hi Tan,
>
> [auto build test ERROR on tip/x86/core]
> [also build test ERROR on v4.6-rc3 next-20160408] [if your patch is applied to
> the wrong git tree, please drop us a note to help improving the system]
>
> url: https://github.com/0day-ci/linux/commits/Tan-Jui-Nee/pinctrl-
> broxton-enable-platform-device-in-the-absent-of-ACPI-
> enumeration/20160411-105542
> config: x86_64-randconfig-n0-04111131 (attached as .config)
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=x86_64
>
> All error/warnings (new ones prefixed by >>):
>
> drivers/mfd/lpc_ich.c:204:22: error: invalid application of 'sizeof' to
> incomplete type 'struct pinctrl_pin_desc'
> .pdata_size = sizeof(apl_pinctrl_pdata),
> ^
> drivers/mfd/lpc_ich.c: In function 'lpc_ich_misc':
> drivers/mfd/lpc_ich.c:1146:4: error: invalid use of undefined type 'struct
> pinctrl_pin_desc'

> apl_pinctrl_pdata.name = kasprintf(GFP_KERNEL, "%u",

> ^
> drivers/mfd/lpc_ich.c:1148:4: error: invalid use of undefined type 'struct
> pinctrl_pin_desc'
> if (apl_pinctrl_pdata.name)
> ^
> drivers/mfd/lpc_ich.c:1148:4: error: invalid use of undefined type 'struct
> pinctrl_pin_desc'
> In file included from include/linux/linkage.h:4:0,
> from include/linux/kernel.h:6,
> from drivers/mfd/lpc_ich.c:63:
> >> include/linux/compiler.h:150:17: error: invalid use of undefined type
> 'struct pinctrl_pin_desc'
> static struct ftrace_branch_data \
> ^
> include/linux/compiler.h:145:23: note: in expansion of macro '__trace_if'
> #define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
> ^
> >> drivers/mfd/lpc_ich.c:1148:4: note: in expansion of macro 'if'
> if (apl_pinctrl_pdata.name)
> ^
> drivers/mfd/lpc_ich.c:1158:7: error: invalid use of undefined type 'struct
> pinctrl_pin_desc'
> apl_pinctrl_pdata.name, ret);
> ^
> drivers/mfd/lpc_ich.c:1160:4: error: invalid use of undefined type 'struct
> pinctrl_pin_desc'
> kfree(apl_pinctrl_pdata.name);
> ^
>
> vim +150 include/linux/compiler.h
>
> 2bcd521a Steven Rostedt 2008-11-21 144 */
> ab3c9c68 Linus Torvalds 2009-04-07 145 #define if(cond, ...) __trace_if(
> (cond , ## __VA_ARGS__) )
> ab3c9c68 Linus Torvalds 2009-04-07 146 #define __trace_if(cond) \
> ab3c9c68 Linus Torvalds 2009-04-07 147 if
> (__builtin_constant_p((cond)) ? !!(cond) : \
> 2bcd521a Steven Rostedt 2008-11-21 148 ({
> \
> 2bcd521a Steven Rostedt 2008-11-21 149 int ______r;
> \
> 2bcd521a Steven Rostedt 2008-11-21 @150 static struct
> ftrace_branch_data \
> 2bcd521a Steven Rostedt 2008-11-21 151
> __attribute__((__aligned__(4))) \
> 2bcd521a Steven Rostedt 2008-11-21 152
> __attribute__((section("_ftrace_branch"))) \
> 2bcd521a Steven Rostedt 2008-11-21 153 ______f = {
> \
>
> :::::: The code at line 150 was first introduced by commit
> :::::: 2bcd521a684cc94befbe2ce7d5b613c841b0d304 trace: profile all if
> conditionals
>
> :::::: TO: Steven Rostedt <sros...@redhat.com>
> :::::: CC: Ingo Molnar <mi...@elte.hu>
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Andy, I will send patch v2 that looks like:

+static int lpc_ich_misc(struct pci_dev *dev, enum lpc_chipsets chipset)
+{

..
+ const char *name;
..

+ /* Fill IRQ resource */
+ res->start = APL_GPIO_IRQ;
+ res->end = res->start;
+ res->flags = IORESOURCE_IRQ;
+

+ name = kasprintf(GFP_KERNEL, "%u", i + 1);
+ if (name)

+ ret = mfd_add_devices(&dev->dev, i,
+ &apl_gpio_devices, 1, NULL, 0, NULL);
+ else
+ ret = -ENOMEM;
+
+warn_continue:
+ if (ret)
+ dev_warn(&dev->dev,
+ "Failed to add Apollo Lake GPIO %s: %d\n",

+ name, ret);
+
+ kfree(name);
..
Please let me know if that isn't the right thing. Thanks.

[Andy Shevchenko]

> Hi Andy, I will send patch v2 that looks like:
>
> +static int lpc_ich_misc(struct pci_dev *dev, enum lpc_chipsets
> chipset)
> +{

> ...
> + const char *name;

This will make things worse.

> Please let me know if that isn't the right thing. Thanks.

Nope. The complain by kbuidbot apparently about specific kernel
configuration. I'm pretty sure it's about CONFIG_PINCTRL=n.

I don't know the best solution here (only add select PINCTRL that sounds
a bit overhead to me), perhaps Lee can advise something.

Perhaps new config option is required for APL like you have

arch/x86:

config X86_INTEL_NON_ACPI
 bool "enable support non-ACPI Intel platforms"
 help
  …

mfd:

config LPC_ICH
        tristate "Intel ICH LPC"
-       depends on PCI
+       depends on X86 && PCI
        select MFD_CORE

+    select P2SB if X86_INTEL_NON_ACPI
+    select PINCTRL if X86_INTEL_NON_ACPI

In the code
#ifdef X86_INTEL_NON_ACPI
#else
#endif

P.S. I don't like this either.

-- 
Andy Shevchenko <andriy.s...@linux.intel.com>
Intel Finland Oy