[PATCH v3 1/4] arm64: qcom: Add support for Qualcomm MSM8916 SoC

[Kumar Gala]

From: Abhimanyu Kapur <abhi...@codeaurora.org>

Add support for Qualcomm MSM8916 SoC in arm64 Kconfig and defconfig.
Enable MSM8916 clock, pin control, and MSM serial driver utilized by
MSM8916 and Qualcomm SoCs in general.

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhi...@codeaurora.org>
---
v3:
* Dropped ARCH_REQUIRE_GPIOLIB, COMMON_CLK_QCOM, and SOC_BUS
* Updated defconfig related to dropping various Kconfig options

v2:
* Dropped CONFIG_ARCH_QCOM_MSM8916, just use CONFIG_ARCH_QCOM
* Updated defconfig related to dropping CONFIG_ARCH_QCOM_MSM8916

arch/arm64/Kconfig | 6 ++++++
arch/arm64/configs/defconfig | 6 ++++++
2 files changed, 12 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e973..610965dd 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -177,6 +177,12 @@ config ARCH_MEDIATEK
help
Support for Mediatek MT65xx & MT81xx ARMv8 SoCs

+config ARCH_QCOM
+ bool "Qualcomm Platforms"
+ select PINCTRL
+ help
+ This enables support for the ARMv8 based Qualcomm chipsets.
+
config ARCH_SEATTLE
bool "AMD Seattle SoC Family"
help
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index be1f12a..d54a1f6 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_FSL_LS2085A=y
CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_QCOM=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_XGENE=y
@@ -93,11 +94,14 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_PL022=y
+CONFIG_PINCTRL_MSM8916=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_XGENE=y
# CONFIG_HWMON is not set
@@ -127,6 +131,8 @@ CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8916=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PHY_XGENE=y
CONFIG_EXT2_FS=y
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[Kumar Gala]

Add qcom,msm-id and qcom,board-id to allow bootloader to identify which
device tree to boot on the MTP8916 boards.

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 3 +++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++++
2 files changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
index 784ad92..8be101c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -12,10 +12,13 @@

/dts-v1/;

+#include <dt-bindings/arm/qcom-ids.h>
#include "msm8916-mtp.dtsi"

/ {
model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
"qcom,msm8916", "qcom,mtp";
+ qcom,board-id = <QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_DEFAULT>,
+ <QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_MTP8916_SMB1360>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 957486f..41f1c0f 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -14,10 +14,15 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/arm/qcom-ids.h>

/ {
model = "Qualcomm Technologies, Inc. MSM8916";
compatible = "qcom,msm8916";
+ qcom,msm-id = <QCOM_ID_MSM8916 0>,
+ <QCOM_ID_MSM8216 0>,
+ <QCOM_ID_MSM8116 0>,
+ <QCOM_ID_MSM8616 0>;

interrupt-parent = <&intc>;

[Kumar Gala]

Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board. At the current time we only boot up a single processor.

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
---

v3:
* Removed qcom,msm-id and qcom,board-id
* Added top level compat for "qcom,msm8916-mtp-smb1360"

v2:
* Updated to dropping CONFIG_ARCH_QCOM_MSM8916
* Updated to use qcom-ids.h
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/qcom/Makefile | 5 +
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 21 ++++
arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 24 ++++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 184 ++++++++++++++++++++++++++++++
5 files changed, 235 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/Makefile
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8916.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350ca..8517f15 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += qcom

subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
new file mode 100644
index 0000000..360ec4c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
new file mode 100644
index 0000000..784ad92
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -0,0 +1,21 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 and
+* only version 2 as published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+/dts-v1/;
+
+#include "msm8916-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
+ compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
+ "qcom,msm8916", "qcom,mtp";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
new file mode 100644
index 0000000..4d2f073
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -0,0 +1,24 @@
+/* Copyright (c) 2014-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8916.dtsi"
+
+/ {
+ soc {
+ serial@78b0000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
new file mode 100644
index 0000000..957486f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -0,0 +1,184 @@
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8916";
+ compatible = "qcom,msm8916";
+
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x1>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x2>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl@1000000 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ blsp1_uart2_default: blsp1_uart2_default {
+ pinmux {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
+ pinmux {
+ function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ };
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ gcc: qcom,gcc@1800000 {
+ compatible = "qcom,gcc-msm8916";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x1800000 0x80000>;
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b0000 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ };
+
+ timer@b020000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb020000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b021000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb021000 0x1000>,
+ <0xb022000 0x1000>;
+ };
+
+ frame@b023000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb023000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b024000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb024000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b025000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb025000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b026000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb026000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b027000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb027000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b028000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb028000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+};

[Kumar Gala]

The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kernel.

Cc: <devic...@vger.kernel.org>

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
---

Documentation/devicetree/bindings/arm/msm/ids.txt | 65 +++++++++++++++++++++++
include/dt-bindings/arm/qcom-ids.h | 33 ++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/ids.txt
create mode 100644 include/dt-bindings/arm/qcom-ids.h

diff --git a/Documentation/devicetree/bindings/arm/msm/ids.txt b/Documentation/devicetree/bindings/arm/msm/ids.txt
new file mode 100644
index 0000000..9ee8428
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/ids.txt
@@ -0,0 +1,65 @@
+* MSM-ID
+
+The qcom,msm-id entry specifies the MSM chipset and hardware revision. It can
+optionally be an array of these to indicate multiple hardware that use the same
+device tree. It is expected that the bootloader will use this information at
+boot-up to decide which device tree to use when given multiple device trees,
+some of which may not be compatible with the actual hardware. It is the
+bootloader's responsibility to pass the correct device tree to the kernel.
+
+PROPERTIES
+
+- qcom,msm-id:
+ Usage: required
+ Value type: <prop-encoded-array> (<chipset_id, rev_id> [, <c2, r2> ..])
+ Definition:
+ The "chipset_id" consists of three fields as below:
+
+ bits 0-15 = The unique MSM chipset id.
+ bits 16-31 = Reserved. Should be 0
+
+ chipset_id is an exact match value
+
+ The "rev_id" is a chipset specific 32-bit id that represents
+ the version of the chipset.
+
+ The rev_id is a best match id. The bootloader will look for
+ the closest possible patch.
+
+* BOARD-ID
+
+The qcom,board-id entry specifies the board type and revision information. It
+can optionally be an array of these to indicate multiple boards that use the
+same device tree. It is expected that the bootloader will use this information
+at boot-up to decide which device tree to use when given multiple device trees,
+some of which may not be compatible with the actual hardware. It is the
+bootloader's responsibility to pass the correct device tree to the kernel.
+
+PROPERTIES
+
+- qcom,board-id:
+ Usage: required
+ Value type: <prop-encoded-array> (<board_id, subtype_id> [, <b2, s2> ..])
+ Definition:
+ The "board_id" consists of three fields as below:
+
+ bits 31-24 = Unusued.
+ bits 23-16 = Platform Version Major
+ bits 15-8 = Platfrom Version Minor
+ bits 7-0 = Platform Type
+
+ Platform Type field is an exact match value. The Platform
+ Major/Minor field is a best match. The bootloader will look
+ for the closest possible match.
+
+ The "subtype_id" is unique to a Platform Type/Chipset ID. For
+ a given Platform Type, there will typically only be a single
+ board and the subtype_id will be 0. However in some cases board
+ variants may need to be distinquished by different subtype_id
+ values.
+
+ subtype_id is an exact match value.
+
+EXAMPLE:
+ qcom,board-id = <15 2>;
+ qcom,msm-id = <0x1007e 0>;
diff --git a/include/dt-bindings/arm/qcom-ids.h b/include/dt-bindings/arm/qcom-ids.h
new file mode 100644
index 0000000..a18f34e
--- /dev/null
+++ b/include/dt-bindings/arm/qcom-ids.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */

+#ifndef __DT_BINDINGS_QCOM_IDS_H
+#define __DT_BINDINGS_QCOM_IDS_H
+
+/* qcom,msm-id */
+#define QCOM_ID_MSM8916 206
+#define QCOM_ID_APQ8016 247
+#define QCOM_ID_MSM8216 248
+#define QCOM_ID_MSM8116 249
+#define QCOM_ID_MSM8616 250
+
+/* qcom,board-id */
+#define QCOM_BRD_ID(a, major, minor) \
+ (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BRD_ID_##a)
+
+#define QCOM_BRD_ID_MTP 8
+#define QCOM_BRD_ID_DRAGONBRD 10
+#define QCOM_BRD_ID_SBC 24
+
+#define QCOM_BRD_SUBTYPE_DEFAULT 0
+#define QCOM_BRD_SUBTYPE_MTP8916_SMB1360 1
+
+#endif

[Mark Rutland]

Hi Kumar,

> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
> + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
> + "qcom,msm8916", "qcom,mtp";
> +};

No /chosen/stdout-path?

Does your UART driver support earlycon?

[...]

The secondary CPUs need an enable-method. Are you using PSCI or
spin-table?

Which exception level do the CPUs enter the kernel?

> + timer {
> + compatible = "arm,armv7-timer";

This should be "arm,armv8-timer".

> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };

NAK. CNTFRQ should be programmed on all CPUs prior to entering the
kernel, per the boot protocol. You should not need clock-frequency here.

[...]

> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";

This string isn't documented (but seems to be supported by the GIC
driver).

How does this differ from other GIC implementations?

> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
> + };

No GICH, GICV, maintenance interrupt?

Minor nit, but I'd prefer if the reg entries were on individual lines as
happens in other dts.

Thanks,
Mark.

[Kumar Gala]

On Mar 12, 2015, at 12:05 PM, Mark Rutland <mark.r...@arm.com> wrote:

> Hi Kumar,
>
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
>> + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
>> + "qcom,msm8916", "qcom,mtp";
>> +};
>
> No /chosen/stdout-path?

Nope ;).

>
> Does your UART driver support earlycon?

It does.

This is on purpose. We aren’t using either PSCI or spin-table. Right now the dts is for booting on a single core. I can drop CPU1..CPU3 if that helps.

> Which exception level do the CPUs enter the kernel?
>
>> + timer {
>> + compatible = "arm,armv7-timer";
>
> This should be "arm,armv8-timer”.

will change

>
>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
>> + };
>
> NAK. CNTFRQ should be programmed on all CPUs prior to entering the
> kernel, per the boot protocol. You should not need clock-frequency here.

Will drop clock-frequency.

> [...]
>
>> + intc: interrupt-controller@b000000 {
>> + compatible = "qcom,msm-qgic2";
>
> This string isn't documented (but seems to be supported by the GIC
> driver).

There’s a patch posted to add ‘qcom,msm-qgic2’ to the binding doc.

> How does this differ from other GIC implementations?

Not sure the exact details, just that its qcom’s on implementation of the GIC spec.

>
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
>> + };
>
> No GICH, GICV, maintenance interrupt?

Nope.

>
> Minor nit, but I'd prefer if the reg entries were on individual lines as
> happens in other dts.
>
> Thanks,
> Mark.

--

Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Kumar Gala]

Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board. At the current time we only boot up a single processor.

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
---

v4:
* Added chosen node so we dont need to spec everything for earlycon
* fixed up timer node to armv8, dropped clock-frequency

v3:
* Removed qcom,msm-id and qcom,board-id
* Added top level compat for "qcom,msm8916-mtp-smb1360"

v2:
* Updated to dropping CONFIG_ARCH_QCOM_MSM8916
* Updated to use qcom-ids.h
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/qcom/Makefile | 5 +
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 21 ++++

arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 28 +++++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 183 ++++++++++++++++++++++++++++++
5 files changed, 238 insertions(+)

create mode 100644 arch/arm64/boot/dts/qcom/Makefile
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8916.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350ca..8517f15 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += qcom

subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile

new file mode 100644

index 0000000..360ec4c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts

new file mode 100644

index 0000000..784ad92
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -0,0 +1,21 @@

+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 and
+* only version 2 as published by the Free Software Foundation.
+*

+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+/dts-v1/;
+
+#include "msm8916-mtp.dtsi"
+

+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
+ compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
+ "qcom,msm8916", "qcom,mtp";
+};

diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
new file mode 100644
index 0000000..270ba55
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -0,0 +1,28 @@
+/* Copyright (c) 2014-2014, The Linux Foundation. All rights reserved.

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */

+
+#include "msm8916.dtsi"
+
+/ {

+ chosen {
+ stdout-path = &blsp1_uart2;
+ };
+

+ soc {
+ serial@78b0000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi

new file mode 100644
index 0000000..8c8fd49
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -0,0 +1,183 @@
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */

+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+

+/ {

+ model = "Qualcomm Technologies, Inc. MSM8916";
+ compatible = "qcom,msm8916";
+
+ interrupt-parent = <&intc>;
+

+
+ timer {
+ compatible = "arm,armv8-timer";

+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

+ };
+
+ soc: soc {
+ #address-cells = <1>;

+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl@1000000 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;

+ interrupt-controller;

+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";

+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ };

+
+ timer@b020000 {
+ #address-cells = <1>;

+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb020000 0x1000>;

+ clock-frequency = <19200000>;
+

[Mark Rutland]

We won't poke the CPUs without an enable-method, so personally I'm not
too worried either way about having the CPUs listed.

Which of spin-table/psci are you planning on using for SMP support, and
when would that be likely to appear?

Which exception level do CPUs enter the kernel? Even without a
virt-capable GIC booting at EL2 is less work for the FW and gives the
kernel a better chance of fixing things up (e.g. CNTVOFF).

Thanks,
Mark.

[Kumar Gala]

That was my thinking, so left them in.

> Which of spin-table/psci are you planning on using for SMP support, and
> when would that be likely to appear?

We have a qcom specific SMP enablement method for this device. This was one of our first devices so it utilized as much from arm 32-bit as possible.

> Which exception level do CPUs enter the kernel? Even without a
> virt-capable GIC booting at EL2 is less work for the FW and gives the
> kernel a better chance of fixing things up (e.g. CNTVOFF).

I think the enter in EL1.

- k

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Mark Rutland]

> > Which of spin-table/psci are you planning on using for SMP support, and
> > when would that be likely to appear?
>
> We have a qcom specific SMP enablement method for this device. This
> was one of our first devices so it utilized as much from arm 32-bit as
> possible.

Implementation specific enable methods are something we really don't
want to see for arm64. If PSCI is out of the question then a spin-table
shim in your bootloader shouldn't be too hard to implement.

> > Which exception level do CPUs enter the kernel? Even without a
> > virt-capable GIC booting at EL2 is less work for the FW and gives the
> > kernel a better chance of fixing things up (e.g. CNTVOFF).
>
> I think the enter in EL1.

That's unfortunate, but so long as they are consistent, it's not the end
of the world.

Mark.

[Mark Rutland]

> +/ {
> + chosen {
> + stdout-path = &blsp1_uart2;
> + };

It would be good if we had the configuration too (see
Documentation/devicetree/bindings/chosen.txt), as that avoids any
reliance on kernel defaults.

You can refer to an alias, so this could be:

aliases {
serial0 = &blsp1_uart2;
};

chosen {
stdout-path = "serial0:115200n8";
};

..assuming that 115200n8 is correct for your UART, of course.


[...]

> +#include "skeleton.dtsi"

I'd like to get rid of skeleton.dtsi; it causes more problems than it
solves (the address/size cells mismatch is confusing and hidden, people
forget to fill in memory nodes appropriately, etc).

Please remove this include and place appropriate #address-cells and #size-cells here.

I'd strongly recommend going with /#size-cells = <2>; it' will save on a
lot of pain if you need to add PCIe or something with large ranges
later. If things all fall in 4GB within the SoC then have
/soc/#size=cells = <1> and an appropriate /soc/ranges property.

I note this DT doesn't have any memory nodes. Is that an accident or
does the loader fill that in?

If the latter, have an empty node with a comment to that effect.

Mark.

[Catalin Marinas]

On Fri, Mar 13, 2015 at 10:34:54AM +0000, Mark Rutland wrote:
> > > Which of spin-table/psci are you planning on using for SMP support, and
> > > when would that be likely to appear?
> >
> > We have a qcom specific SMP enablement method for this device. This
> > was one of our first devices so it utilized as much from arm 32-bit as
> > possible.
>
> Implementation specific enable methods are something we really don't
> want to see for arm64.

I fully agree (and we've been stating this for over two years).

> If PSCI is out of the question then a spin-table shim in your
> bootloader shouldn't be too hard to implement.

And I guess only WFI cpuidle supported in Linux.

--
Catalin

[Kumar Gala]

On Mar 13, 2015, at 5:52 AM, Mark Rutland <mark.r...@arm.com> wrote:

>> +/ {
>> + chosen {
>> + stdout-path = &blsp1_uart2;
>> + };
>
> It would be good if we had the configuration too (see
> Documentation/devicetree/bindings/chosen.txt), as that avoids any
> reliance on kernel defaults.
>
> You can refer to an alias, so this could be:
>
> aliases {
> serial0 = &blsp1_uart2;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
>

> ...assuming that 115200n8 is correct for your UART, of course.
>
>
> […]

Where is the code that actually handles this parsing? I’m not see it in early_init_dt_scan_chosen_serial and I don’t believe fdt_path_offset does anything special with ‘:'

>
>> +#include "skeleton.dtsi"
>
> I'd like to get rid of skeleton.dtsi; it causes more problems than it
> solves (the address/size cells mismatch is confusing and hidden, people
> forget to fill in memory nodes appropriately, etc).
>
> Please remove this include and place appropriate #address-cells and #size-cells here.
>
> I'd strongly recommend going with /#size-cells = <2>; it' will save on a
> lot of pain if you need to add PCIe or something with large ranges
> later. If things all fall in 4GB within the SoC then have
> /soc/#size=cells = <1> and an appropriate /soc/ranges property.
>
> I note this DT doesn't have any memory nodes. Is that an accident or
> does the loader fill that in?

it was coming out of skeleton.dtsi

>
> If the latter, have an empty node with a comment to that effect.

I’ll kill off usage of skeleton.dtsi

- k

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Kumar Gala]

Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board. At the current time we only boot up a single processor.

Signed-off-by: Kumar Gala <ga...@codeaurora.org>
---

v5:
* killed use of skeleton, moved to addr/size cells both being 2
* Added serial alias in prep of being able to spec uart params
in chosen node

v4:
* Added chosen node so we dont need to spec everything for earlycon
* fixed up timer node to armv8, dropped clock-frequency

v3:
* Removed qcom,msm-id and qcom,board-id
* Added top level compat for "qcom,msm8916-mtp-smb1360"

v2:
* Updated to dropping CONFIG_ARCH_QCOM_MSM8916
* Updated to use qcom-ids.h

arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/qcom/Makefile | 5 +
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 21 ++++

arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 32 +++++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 195 ++++++++++++++++++++++++++++++
5 files changed, 254 insertions(+)

index 0000000..8dbb77f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -0,0 +1,32 @@

+/* Copyright (c) 2014-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8916.dtsi"
+
+/ {

+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";

+ };
+
+ soc {
+ serial@78b0000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
new file mode 100644

index 0000000..45ceca6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -0,0 +1,195 @@

+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+

+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8916.h>
+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8916";
+ compatible = "qcom,msm8916";
+
+ interrupt-parent = <&intc>;
+

+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases { };
+
+ chosen { };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+

+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc: soc {

+ #address-cells = <1>;

+ #address-cells = <1>;

[Mark Rutland]

On Fri, Mar 13, 2015 at 03:50:42PM +0000, Kumar Gala wrote:
>
> On Mar 13, 2015, at 5:52 AM, Mark Rutland <mark.r...@arm.com> wrote:
>
> >> +/ {
> >> + chosen {
> >> + stdout-path = &blsp1_uart2;
> >> + };
> >
> > It would be good if we had the configuration too (see
> > Documentation/devicetree/bindings/chosen.txt), as that avoids any
> > reliance on kernel defaults.
> >
> > You can refer to an alias, so this could be:
> >
> > aliases {
> > serial0 = &blsp1_uart2;
> > };
> >
> > chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > ...assuming that 115200n8 is correct for your UART, of course.
> >
> >
> > […]
>
> Where is the code that actually handles this parsing? I’m not see it
> in early_init_dt_scan_chosen_serial and I don’t believe
> fdt_path_offset does anything special with ‘:'

Take a look at commit 7914a7c5651a5161 ("of: support passing console options with
stdout-path").

Early on of_alias_scan will find the options and in of_console_check
we'll call add_preferred_console as appropriate. That'll be called in
uart_add_one_port.

> I’ll kill off usage of skeleton.dtsi

Cheers.

Mark.

[Kumar Gala]

On Mar 13, 2015, at 11:25 AM, Mark Rutland <mark.r...@arm.com> wrote:

> On Fri, Mar 13, 2015 at 03:50:42PM +0000, Kumar Gala wrote:
>>
>> On Mar 13, 2015, at 5:52 AM, Mark Rutland <mark.r...@arm.com> wrote:
>>
>>>> +/ {
>>>> + chosen {
>>>> + stdout-path = &blsp1_uart2;
>>>> + };
>>>
>>> It would be good if we had the configuration too (see
>>> Documentation/devicetree/bindings/chosen.txt), as that avoids any
>>> reliance on kernel defaults.
>>>
>>> You can refer to an alias, so this could be:
>>>
>>> aliases {
>>> serial0 = &blsp1_uart2;
>>> };
>>>
>>> chosen {
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> ...assuming that 115200n8 is correct for your UART, of course.
>>>
>>>
>>> […]
>>
>> Where is the code that actually handles this parsing? I’m not see it
>> in early_init_dt_scan_chosen_serial and I don’t believe
>> fdt_path_offset does anything special with ‘:'
>
> Take a look at commit 7914a7c5651a5161 ("of: support passing console options with
> stdout-path").
>
> Early on of_alias_scan will find the options and in of_console_check
> we'll call add_preferred_console as appropriate. That'll be called in
> uart_add_one_port.

Ok, but earlycon dt code doesn’t utilize this, as its setup is before we unflatten the dt.

So it breaks earlycon parsing right now, I’ll look at fixing that.

- k

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Stanimir Varbanov]

multi line comment rules

multi line comment rules and 2014-2015

Why don't describe this as:

&blsp1_uart2 {
status = "okay";
pinctrl-names = xxxx;
....
};

it looks more readable and obvious. This is what the other boards doing
as well.

<snip>

--
regards,
Stan

[Kumar Gala]

I find the way it is more explicit and obvious, plus it works for cases that don’t have a label associated with them.

I’ll fixup the multiline comment issues.

- k

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project