hpet as nmi watchdog

[Andriy Gapon]

I toyed a little bit with an idea of using a HPET timer as an NMI watchdog.
The idea is that a HPET timer is somehow configured to generate an NMI when it
fires. The timer normally would not fire, of course, as it is constantly being
reprogrammed to some future time as is the case for all watchdogs.

I have written some proof of concept code using two approaches. One approach is
to use the "FSB" (MSI-like) mode of a HPET timer and program a corresponding FSB
data register (HPET_TIMER_FSB_VAL) with a value that sets NMI delivery mode
using the IO-APIC specification. The other approach is to use legacy interrupt
mode for the HPET timer and program a corresponding IO-APIC pin for NMI deliver
mode.
In both cases I haven't got a desired result - instead of an NMI a test system
gets reset when the timer fires. I wonder if this is a quirk of my old hardware
(HPET in AMD SB7xx, family 10h processor) or if my idea is a non-starter.

Thoughts, suggestions?..
Thanks!
--
Andriy Gapon
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[John Baldwin]

On Tuesday, March 08, 2016 01:37:33 PM Andriy Gapon wrote:
>
> I toyed a little bit with an idea of using a HPET timer as an NMI watchdog.
> The idea is that a HPET timer is somehow configured to generate an NMI when it
> fires. The timer normally would not fire, of course, as it is constantly being
> reprogrammed to some future time as is the case for all watchdogs.
>
> I have written some proof of concept code using two approaches. One approach is
> to use the "FSB" (MSI-like) mode of a HPET timer and program a corresponding FSB
> data register (HPET_TIMER_FSB_VAL) with a value that sets NMI delivery mode
> using the IO-APIC specification. The other approach is to use legacy interrupt
> mode for the HPET timer and program a corresponding IO-APIC pin for NMI deliver
> mode.
> In both cases I haven't got a desired result - instead of an NMI a test system
> gets reset when the timer fires. I wonder if this is a quirk of my old hardware
> (HPET in AMD SB7xx, family 10h processor) or if my idea is a non-starter.

This is an interesting idea. You could also use one of the other timers (8254,
etc.) as a watchdog by setting the I/O APIC pin to NMI as well. It maybe that
for the MSI case the chipset treats the NMI delivery mode as an error, hence
the reset. :-/

--
John Baldwin

[Andriy Gapon]

On 23/05/2016 23:44, John Baldwin wrote:
> On Tuesday, March 08, 2016 01:37:33 PM Andriy Gapon wrote:
>>
>> I toyed a little bit with an idea of using a HPET timer as an NMI watchdog.
>> The idea is that a HPET timer is somehow configured to generate an NMI when it
>> fires. The timer normally would not fire, of course, as it is constantly being
>> reprogrammed to some future time as is the case for all watchdogs.
>>
>> I have written some proof of concept code using two approaches. One approach is
>> to use the "FSB" (MSI-like) mode of a HPET timer and program a corresponding FSB
>> data register (HPET_TIMER_FSB_VAL) with a value that sets NMI delivery mode
>> using the IO-APIC specification. The other approach is to use legacy interrupt
>> mode for the HPET timer and program a corresponding IO-APIC pin for NMI deliver
>> mode.
>> In both cases I haven't got a desired result - instead of an NMI a test system
>> gets reset when the timer fires. I wonder if this is a quirk of my old hardware
>> (HPET in AMD SB7xx, family 10h processor) or if my idea is a non-starter.
>
> This is an interesting idea. You could also use one of the other timers (8254,
> etc.) as a watchdog by setting the I/O APIC pin to NMI as well. It maybe that
> for the MSI case the chipset treats the NMI delivery mode as an error, hence
> the reset. :-/
>

I got this working on the same hardware using HyperTransport definition of the
NMI message type (see my recent post in this mailing list). Both in the FSB/MSI
and I/O-APIC modes.

--
Andriy Gapon