Huge latency for some instructions

[Alireza Heidar-Barghi]

Hello,

I have noticed that some of the instructions show huge latencies at their retire cycle when I am simulating some multi-threaded applications using ESESC. For example, 11188674 cycles. Further investigation revealed that some instructions retire very long after their fetch cycle. Also, I saw "resume 0 -> 0" and the like (i.e., for other fids) before the stalled instruction retires.

I have a couple of questions:

1) Have you ever experienced this situation or somebody reported this situation to you? That is, is there a known bug?

2) Is there a quick fix for that?

I believe there is an issue in connecting the emulator and timing simulator. I looked at this function QEMUReader::queueInstruction() in ./emul/libqemuint/QEMUReader.cpp, which was very complicated to understand.

BTW, the simulator version I am using is 2013-ARMv7.

Any help is greatly appreciated.

Thank you very much in advance,

Alireza

[Jose Renau]

 If you are doing a context switch, some instructions got fetched but not executed until they come back. This can result in insane latency for that instruction.

 If there are not context switches, that should not happen (unless there is a bug)

--

Computer Engineering

UC Santa Cruz

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[Alireza Heidar-Barghi]

Hi,

Thanks for the reply.

There is no context switch. 

How could I fix that? Is the function QEMUReader::queueInstruction() a right point to start? If yes, could you or anybody of your teammates please walk me through this function?

Thanks

[Jose Renau]

 If you find the bug and solve it, I would be more than happy to post it in github and give you credit.

--

Computer Engineering

UC Santa Cruz

[Bilal Siddiqui]

I have a similar problem in that the Resource Objects all seem to use the same 1 cycle latency for every instruction/FU.
Did you come across a similar observation ?

I am trying to spontaneously manipulate the instruction scheduling and execution time to simulate re-computations. Would you happen to know where the latencies for instructions are being implemented ?