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ESESC is a fast architectural simulator. It provides an integrated performance, power and temperature modelling tool chain, supporting single and multicore configurations.

ESESC source code is available here: https://github.com/masc-ucsc/esesc
Blog posts and tutorials are posted here: http://masc.cse.ucsc.edu/esesc/

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Gabriel Southern, … Jose Renau10

2/5/19

ESESC switching to MIPS64

This is an old checkout, when you do a git pull to the latest, you'll see different directories (

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ESESC switching to MIPS64

This is an old checkout, when you do a git pull to the latest, you'll see different directories (

2/5/19

Gabriel Southern3

6/15/14

ESESC Tutorial at ISCA on June 14

Thanks to everyone who attended the tutorial. We hope it was useful and look forward to seeing new

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ESESC Tutorial at ISCA on June 14

Thanks to everyone who attended the tutorial. We hope it was useful and look forward to seeing new

6/15/14

4/19/20

New discussion group

Hello, I am going to deprecate this (not so use) mailing list. I created a new gitter esesc channel

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New discussion group

Hello, I am going to deprecate this (not so use) mailing list. I created a new gitter esesc channel

4/19/20

ZHAO KANG, Jose Renau2

11/12/19

Trying to enablePower with mips64

Alamelu was the last student that used the power model. The issue is that has not been used in

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Trying to enablePower with mips64

Alamelu was the last student that used the power model. The issue is that has not been used in

11/12/19

ZHAO KANG, Jose Renau2

11/7/19

Trying to support mips64r2, but nBranches is not accurate

Current esesc uses mipsR6. My guess is that you need to extend translate.c in qemu to also instrument

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Trying to support mips64r2, but nBranches is not accurate

Current esesc uses mipsR6. My guess is that you need to extend translate.c in qemu to also instrument

11/7/19

aaku...@ncsu.edu, Jose Renau2

4/12/19

Oracle Branch Predictor

the BPOracle is just for the Taken/No-Taken predictor. If both BPOracle and BTB are oracle, you get

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Oracle Branch Predictor

the BPOracle is just for the Taken/No-Taken predictor. If both BPOracle and BTB are oracle, you get

4/12/19

Alireza Heidar-Barghi, Jose Renau2

3/15/19

Simulator freezes for 8-threaded application at some point!

I do not know. I have not run ARMv7 for Years. We use MIPS and RISCV. I tried MIPS with the FFT and

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Simulator freezes for 8-threaded application at some point!

I do not know. I have not run ARMv7 for Years. We use MIPS and RISCV. I tried MIPS with the FFT and

3/15/19

aaku...@ncsu.edu, Jose Renau2

3/5/19

Doubts in BP working

To restrict the fetch prediction per boundary. In hardware there tends to be no time to compute the

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Doubts in BP working

To restrict the fetch prediction per boundary. In hardware there tends to be no time to compute the

3/5/19

aaku...@ncsu.edu, Jose Renau2

2/26/19

Understand branch predictor configuration in simu.conf.samurai

There are 2 branch predictors because processors can have a fast and a slow branch predictor Jose

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Understand branch predictor configuration in simu.conf.samurai

There are 2 branch predictors because processors can have a fast and a slow branch predictor Jose

2/26/19

aaku...@ncsu.edu, Jose Renau2

2/25/19

Help for running Crafty on ESESC

crafty reads the input setup from stdin (not as an argument) ./esesc <crafty.input Jose Renau

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Help for running Crafty on ESESC

crafty reads the input setup from stdin (not as an argument) ./esesc <crafty.input Jose Renau

2/25/19

aaku...@ncsu.edu

2/4/19

Hello Everybody, I am new to ESESC. I wanted to know how to run MIPS on ESESC and QEMU? If you have

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Hello Everybody, I am new to ESESC. I wanted to know how to run MIPS on ESESC and QEMU? If you have

2/4/19

naveed ul Mustafa, aaku...@ncsu.edu3

1/31/19

Compiling ESESC for the first time

I don't remember how I resolved the error as I used ESESC 2 years ago. Following link might be

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Compiling ESESC for the first time

I don't remember how I resolved the error as I used ESESC 2 years ago. Following link might be

1/31/19

aaku...@ncsu.edu

1/31/19

Error while running ESESC

Hello, I am facing this error when i am following the instructions on this page: https://github.com/

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Error while running ESESC

Hello, I am facing this error when i am following the instructions on this page: https://github.com/

1/31/19

aaku...@ncsu.edu, Jose Renau8

1/31/19

Error in make during compilation

my mistake, a bug because it should initialize everything to zero (feel free to create a pull request

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Error in make during compilation

my mistake, a bug because it should initialize everything to zero (feel free to create a pull request

1/31/19

aaku...@ncsu.edu, Jose Renau2

1/30/19

Maybe it is a cmake version problem. If you use the latest esesc, we run regression with Travis and a

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Maybe it is a cmake version problem. If you use the latest esesc, we run regression with Travis and a

1/30/19

Goverdhan Reddy, … Jose Renau6

10/18/18

Designing hardware accelerator

Check the code inside AccProcessor.cpp. The idea is that you can generate traffic to the caches like

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Designing hardware accelerator

Check the code inside AccProcessor.cpp. The idea is that you can generate traffic to the caches like

10/18/18

Alireza Heidar-Barghi

6/25/17

Blocking MSHR problem for shared L2 cache

Hello, I have noticed two requests are running in parallel for the shared L2 cache with blocking MSHR

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Blocking MSHR problem for shared L2 cache

Hello, I have noticed two requests are running in parallel for the shared L2 cache with blocking MSHR

6/25/17

Alireza Heidar-Barghi, … Bilal Siddiqui5

4/13/17

Huge latency for some instructions

I have a similar problem in that the Resource Objects all seem to use the same 1 cycle latency for

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Huge latency for some instructions

I have a similar problem in that the Resource Objects all seem to use the same 1 cycle latency for

4/13/17

3/23/17

Possible Compilation Problems

The Debug build fails for the master branch with the following (macro expansion problems) while the

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Possible Compilation Problems

The Debug build fails for the master branch with the following (macro expansion problems) while the

3/23/17

3/2/17

What address translation mechanisms are used in ESESC?

Hi, At each level of the cache hierarchy, what address translation mechanisms (VIVT, PIPT, VIPT, PIVT

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What address translation mechanisms are used in ESESC?

Hi, At each level of the cache hierarchy, what address translation mechanisms (VIVT, PIPT, VIPT, PIVT

3/2/17

Yomi Karthik, Jose Renau2

2/3/17

CUDA kernel in ESESC

Not an easy project. It took at PhD student over 2 Years to get CUDA running with ESESC. On 2/3/2017

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CUDA kernel in ESESC

Not an easy project. It took at PhD student over 2 Years to get CUDA running with ESESC. On 2/3/2017

2/3/17

Alireza Heidar-Barghi, Jose Renau2

1/30/17

Replacing cache coherency protocol MOESI (ARM-version ESESC) with MESI (MIPS-version ESESC)

I would recommend to switch to the MIPS version as it has many patches in coherence, and it has been

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Replacing cache coherency protocol MOESI (ARM-version ESESC) with MESI (MIPS-version ESESC)

I would recommend to switch to the MIPS version as it has many patches in coherence, and it has been

1/30/17

Yomi Karthik, Jose Renau2

1/18/17

Understanding syscalls on ESESC

All the syscalls are managed through qemu. Check misc/qemu/linux-user/syscall.c A malloc will not do

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Understanding syscalls on ESESC

All the syscalls are managed through qemu. Check misc/qemu/linux-user/syscall.c A malloc will not do

1/18/17

Goverdhan Reddy

1/16/17

Understanding syscalls and function calls in ESESC

Hi, I am interested in knowing how syscalls and function calls are handled on ESESC. For example, how

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Understanding syscalls and function calls in ESESC

Hi, I am interested in knowing how syscalls and function calls are handled on ESESC. For example, how

1/16/17

10/27/16

QEMU is pthreaded Each pthread is mapped to a different CPU Instructions are dynamically created, so

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QEMU is pthreaded Each pthread is mapped to a different CPU Instructions are dynamically created, so

10/27/16

veejee, … Bilal Siddiqui13

9/28/16

Makefile:75: recipe for target 'all' failed

Good news. I have managed to compile and run ESESC on my Core 2 Duo machine. I used the following

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Makefile:75: recipe for target 'all' failed

Good news. I have managed to compile and run ESESC on my Core 2 Duo machine. I used the following

9/28/16

Anthony Cabrera, Jose Renau2

9/27/16

Problem with blackscholes benchmark

One difference is the ROI (region if interest) behavior. The default esesc has no roiOnly set (set to

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Problem with blackscholes benchmark

One difference is the ROI (region if interest) behavior. The default esesc has no roiOnly set (set to

9/27/16

Chao Peng, Jose Renau2

8/7/16

How to set the same configurations as the HPCA2013 paper?

The code has evolved since HPCA2013, but the default settings are the closest for sampling. On 8/6/

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How to set the same configurations as the HPCA2013 paper?

The code has evolved since HPCA2013, but the default settings are the closest for sampling. On 8/6/

8/7/16

kira...@umn.edu

7/23/16

Getting Dynamic Power Numbers of Cache as Zero

Forgive me if this is a silly question but I just started using ESESC and ran some sample simulations

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Getting Dynamic Power Numbers of Cache as Zero

Forgive me if this is a silly question but I just started using ESESC and ran some sample simulations

7/23/16

veejee, Chao Peng4

7/17/16

Power enabled doesn't work

Thanks a lot! 2016-07-16 1:58 GMT+08:00 veejee <vijayalaksh...@gmail.com>: Hi, Yes, I

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Power enabled doesn't work

Thanks a lot! 2016-07-16 1:58 GMT+08:00 veejee <vijayalaksh...@gmail.com>: Hi, Yes, I

7/17/16

Chao Peng, … Gabriel Southern4

7/13/16

How to run the ARM executables or benchmark in ESESC?

Thanks so much! I will try to see the old version. Chao 2016-07-14 2:55 GMT+08:00 Gabriel Southern

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How to run the ARM executables or benchmark in ESESC?

Thanks so much! I will try to see the old version. Chao 2016-07-14 2:55 GMT+08:00 Gabriel Southern

7/13/16

6/22/16

Adding data section to packets

Hello everybody. As you know, ESESC simulates metadata (eg, address) and does not include data

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Adding data section to packets

Hello everybody. As you know, ESESC simulates metadata (eg, address) and does not include data

6/22/16

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