Regarding RISC-V architecture support in the RTOS Embox

[Suraj Sonawane]

Hey @Anton Bondarev@zhmulin...@yandex.ru

I'm currently working on a proposal for the OSPP project to improve RISC-V architecture support in the RTOS Embox. To do this, I've been researching the existing work on adding RISC-V architecture support for Embox. 

I've looked into the following PRs:

• add initial risc-v support #1512
  

•  riscv: add vfork and ptregs_jmp #1652

• Riscv #1648

• RISC-V #1611
• Clean risc-v support #1622
• add riscv64 #2053 
• Riscv #2070

From this, I've found that some support has already been added.
In the project description, there's a mention of adding virtual memory support (mapping physical memory into the virtual address space) and I've also found an issue related to sifive-plic.  

Can you please provide more details on what you would like to see accomplished during this 3-month OSPP program (for adding RISC-V architecture support in the RTOS Embox)?

[Anton Bondarev]

Hi ,

We suggested the common direction. We hope a student(s) who will work on it can improve riscv parts like PLIC, CLINT, floating point support, PMP, and others, but it is not a strict wish list.

Regards,

Anton 

вс, 19 мая 2024 г., 12:13 Suraj Sonawane <surajson...@gmail.com>:

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[Suraj Sonawane]

Thank you for this information.

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