Hello @Anton Bondarev & @zhmulin...@yandex.ru
I hope this email finds you well. I've attached my proposal for RISC-V architecture support for Embox[Link]. Your feedback on it would be greatly appreciated. I've added commentator access so you can add comments directly also.
This is not the final proposal; two components (CLIENT, FPU) still need to be added, and I will also make further modifications.
I apologize for the delay in sending this over, as my exams started last week and I have been quite occupied with them.
Additionally, anyone from the community is welcome to add their feedback.
Thank you for your time.
Best regards,
Suraj Sonawane
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I just started with the items mentioned in the project description. I reviewed everything thoroughly and explored numerous GitHub repositories, articles, and manuals to understand and gather references related to the project.
I had a format in mind for the proposal, and to refine this, I referred to many GSoC proposals and YouTube videos available online. You can simply search "GSoC accepted proposals" on Google for examples.
From the available resources, I listed the things that need to be implemented and added detailed information about each. Best regards, Suraj Sonawane
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I have completed all the remaining components in the proposal. Could you please review it and let me know if there are any additional details you are expecting? I plan to submit the proposal today.
Additionally, I wanted to update you on my progress regarding the SiFive PLIC issue. I have tested SiFive platforms using QEMU, thoroughly studied the riscv_plic.c code, and am currently in the process of implementing the solution. If I encounter any doubt during the implementation, I will reach out to you for clarification. I will also share the code Pull Request (PR) for your review shortly.
Furthermore, I'd like to inform you that due to my ongoing exams until June 13th, I wasn't able to work continuously on the issue.
Best regards,
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