Webinar - Verificacion usando UVM. Uniformly Distributed Maxima over Configurable Windows

[Guillermo Guichal]

Para los que esten involucrados en verificacion de FPGAs o ASICs, les paso información de un webinar que presentaran dos de nuestras desarrolladoras.

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Random Variable Generation: Uniformly Distributed Maxima over Configurable Windows

Inscripción: https://luma.com/0mehqrks

​In verification, when testing a device with random inputs, it is important to ensure that the values used span the entire operational range. This is typically accomplished by using a uniform distribution for the input stimulus, often with additional weighting on boundary values to more effectively test corner cases.

​In many digital signal processing (DSP) algorithms, it is common to operate with the maximum value of a set of input signals. For this specific case, it is desirable that the distribution of the input stimuli be such that the distribution of the maximum value, measured over a window of length N, is uniform.

​In this Webinar, we will analyze this problem and present the implementation of a class that generates stimulus with this characteristic. Specifically, we will determine what distribution the random variable y must have in order for max(y) to follow a uniform distribution within a range of length N and then we will analyze possible implementations of this solution in Systemverilog.