Re: Digest for electricvlsi@googlegroups.com - 1 update in 1 topic

[Alexandre Rusev]

Attachments are filtered out by the maillist. Right?

Send please a download link if you want that anyone could see your example...

On Tue, Jul 20, 2021 at 9:30 AM <electr...@googlegroups.com> wrote:

electr...@googlegroups.com

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• MOSFET SWITCH - 1 Update

MOSFET SWITCH

Jerome FOLLA KAMDEM <jfolla...@gmail.com>: Jul 20 01:54AM +0200 Hi, Please ,currently I use switmod device (voltage controlled switch) as a switch in LTspice. But, I am facing some issues about how to substitute that component with a single MOSFET, playing the same role. Could someone help me please ? Find attached herewith the switch. Thanks for your attention. Regards   Jerome

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[Gavin Abo]

I currently don't have an answer to the MOSFET question, but I did receive the switmod.asc file that was attached.

Though, I have "My membership settings" set to "Each email" in my Google account.  Refer to the "Change your own subscription settings" section on the page at:

https://support.google.com/groups/answer/2464926?hl=en

It looks like you are probably subscribed as Digest which might be why you did not receive it.

However, if you go to the following direct link to the conversation post in a web browser, you will likely find it there as an attachment that is downloadable:

https://groups.google.com/g/electricvlsi/c/sWZgPTUG7Ws/m/K6U1jpCcAQAJ

[Alexandre Rusev]

Jerome, what exactly you are trying to do?

Do you have a testbenct schematics for LTSpice which contains signal sources

and output measurements?

Need a testbench containing 2 variants of schematics:

 1.  using swithcmod

 2. using mosfet

Then two outputs are compared one vs. another.

Any mosfet may behave very differently from switch if operating in linear mode

(triode region of  Id(Vgd) characterics) , when Vgd < threshold voltage and so on.

Using transistors as transmission gates has specifics, so that building mux-es only from transmission gates (without amplifiers) may be quite tricky.

Ok, if you need to model two stage trigger this way, you probably need to add RC

between switches due to avoid undefinities of "zero duration time switching" 

Bring your testbench schematics and simulation results "to the studio";) to make someone able to alanlyze your results!

Version 4
SHEET 1 2740 696
WIRE 80 -848 80 -912
WIRE 480 -784 480 -848
WIRE 656 -784 656 -848
WIRE 80 -736 80 -768
WIRE 160 -736 80 -736
WIRE 192 -736 160 -736
WIRE 464 -736 352 -736
WIRE 592 -736 544 -736
WIRE 640 -736 592 -736
WIRE 816 -736 720 -736
WIRE 80 -704 80 -736
WIRE 80 -560 80 -624
FLAG 160 -736 Vtrip
FLAG 80 -912 VDD
IOPIN 80 -912 In
FLAG 80 -560 0
FLAG 528 -784 Vtrip
FLAG 704 -784 Vtrip
FLAG 816 -736 P3
IOPIN 816 -736 BiDir
FLAG 352 -736 P1
IOPIN 352 -736 BiDir
FLAG 480 -848 clk1
IOPIN 480 -848 In
FLAG 656 -848 clk2
IOPIN 656 -848 In
FLAG 592 -736 P2
IOPIN 592 -736 BiDir
SYMBOL sw 560 -736 R90
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S1
SYMBOL res 64 -720 R0
SYMATTR InstName R1
SYMATTR Value 100Meg
SYMBOL res 64 -864 R0
SYMATTR InstName R2
SYMATTR Value 100Meg
SYMBOL sw 736 -736 R90
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S3
TEXT 488 -568 Left 0 !.model switmod SW