Behavorial VHDL implementation

[Alexandre Rusev]

Why don't to try to implement behavorial VHDL support basing on
sourcecode of VHDL-to-gates compiler (converter from behavioral to
schematic VHDL)
available in Alliance CAD tool?
(http://www-asim.lip6.fr/recherche/alliance/)

As a first step their command line tool may be integrated with
electric VHDL-to-silicone compiler. After that the C-source could be
ported to Java.

As compile-compiler for interpreting VHDL Metamata JavaCC may be used
for example.

[Dmitry Nadezhin]

Yes, I guess that the synthesis from behavioral VHDL/Verilog description is interesting feature for many users.
But what is your suggestion ?  Do you want to implement this feature or this is a request for somebody to implement  ?

  -Dima

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[Alexandre Rusev]

Dmitry Nadezhin wrote:
> Yes, I guess that the synthesis from behavioral VHDL/Verilog description is
> interesting feature for many users.
> But what is your suggestion ? Do you want to implement this feature or this
> is a request for somebody to implement ?

I think that the right implementation would require of more than one
person effort.
I considered thinking about to do something ;)

My "plan" includes following, yet I guess that several enhancemets are
to be done with Electric code and tested independently from
"Behavorial VHDL implementation":

[1] Analyze the algorithms of mapping to gates used in Alliance CAD on
respect to
applicability for Electiric workflow, carry out experiments with
compiling Alliance tool
output in Electric.
[2] Contrive an abstract interface appropriate bot for mapper-to-gates
and mapper-to-techlibrary-gates.
(I thing that taking into account mapping to technology library
instead of simple gates
is needed to support FPGA)
[3] Design HDL parser (using JavaCC for example) and integrate it into
Electric.
First appropriate BNF file must be selected is to be translated
to JavaCC language...
(this is needed due to use the same parser for behavioral and
schematic VHDL)
[4] Extract Alliance mapper-to-gates algorithm and integrate it to
newly introduced parser.
[5] Integrate new parser with current implementation of Electric
schematic VHDL to gates mapper


[1] and [3] would be better to perform at first due to implement it
taking into account rwhat is needed by Alliance and Electric
algorithms

>

Alex

[Dmitry Nadezhin]

I created a project "Electric Alliance" on java.net with such a description:
Electric and Alliance are names of two open source VLSI CAD systems.
This project evaluates project flow from VHDL behavioral description to layout
using combination of Alliance and Electric tools.

I invite anybody interested in this topic to join the project by emailing me or Alexandre Rusev.

The new projects on java.net are private by default. We shall request
communit...@java.net to make "Electric Alliance"  public as soon as we prepare minimal contents
on Web pages of this project.

  -Dima

--

[Dmitry Nadezhin]

The project "Electric Alliance" on java.net is public now:

http://java.net/projects/electric-alliance

  -Dima