You do not have permission to delete messages in this group
Copy link
Report message
Show original message
Either email addresses are anonymous for this group or you need the view member email addresses permission to view the original message
to electr...@googlegroups.com
Hi, I noticed when creating an nMOS transistor, Electric will create the spice deck differently for the schematic compared to the layout. Don't have this problem with pMOS. See below, drain source are backwards for the spice deck of the layout. Anyone know why or how to correct this?