PCI Basics # 2

[Mukund]

Hi All,

 

During Last session we have seen How PCI PCI-X and PCIe looks like with some basic information for the same.

 

Today we are going to float information about PCI signals.

 

On PCI when communication happens one device treats as Master and another one as Target.

 

Master : The device which initiates read or write transaction and which drives the clock through out operation.

Target : The device with which Master performs read or write and which acts as a Slave.

Below figure shows the Master-Target signal details.

 

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System Signals :

CLK

• Clock provides the timing reference for all transfers on the PCI bus.
• The minimum frequency of the CLK signal is specified at 0 Hz permitting CLK to be "suspended" for power saving purposes.

RST#

• Reset is driven active low to cause a hardware reset of a PCI device.
• The reset shall cause a PCI device's configuration registers, state machines, and output signals to be placed in their initial state.
• RST# is asserted and deasserted asynchronously to the CLK signal.
  

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Address and Data Signals :

AD[31:0]

• Address and Data are multiplexed onto these pins.
• AD[31:0] transfers a 32-bit physical address during "address phases", and transfers 32-bits of data information during "data phases".
• When both IRDY# and TRDY# are low, the initiator captures the data and the transaction is completed.

C/BE[3:0]#

• Bus Command and Byte Enables are multiplexed onto these pins.
• During the address phase of a transaction these signals carry the bus command that defines the type of transfer to be performed.
• During the data phase of a transaction these signals carry byte enable information.

PAR

• Parity is even parity over the AD[31:0] and C/BE[3:0]# signals.
• Even parity implies that there is an even number of '1's on the AD[31:0], C/BE[3:0]#, and PAR signals.

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Interface Control Signals :

FRAME#

• Cycle Frame is driven low by the initiator to signal the start of a new bus transaction.

IRDY#

• Initiator Ready is driven low by the initiator as an indication that it is ready to complete current data phase of the transaction.
• During writes it indicates the initiator has placed valid data on AD[31:0].
• During reads it indicates the initiator is ready to accept data on AD[31:0].
• Once asserted, the initiator holds IRDY# low until TRDY# is driven low to complete the transfer, or the target uses the STOP# signal to terminate without performing the data transfer. IRDY# permits the initiator to insert wait states as needed to slow the data transfer.

TRDY#

• Target Ready is driven low by the target as an indication it is read to complete the current data phase of the transaction.
• During writes it indicates the target is ready to accept data on AD[31:0].
• During reads it indicates the target has placed valid data on the AD[31:0] signals.
• Once asserted, the target holds TRDY# low until IRDY# is driven low to complete the transfer.
• TRDY# permits the target to insert wait states as needed to slow the data transfer.

DEVSEL#

• DEVSEL# is driven active low by a PCI target when it detects its address on the PCI bus.
• DEVSEL# may be driven one, two, or three clocks following the address phase.
• DEVSEL# must be asserted with or prior to the clock edge in which the TRDY# signal is asserted.
• Once DEVSEL# has been asserted, it cannot be deasserted until the last data phase has completed, or the target issues a target abort.
• If the initiator never receives an active DEVSEL# it terminates the transaction in what is termed a master abort.
  

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In further session we will see PCI read write signal and types.

 

Also attached snap shot of figures if facing issue while viewing in mail.

 

Let us know if require further information if any.