Make use of BIT(x) wherever register operations on a bit level were
done.
The macro is not adapted to other macros that describe register masks,
since that would violate the schemantic meaning of BIT(x).
Signed-off-by: Benedikt Niedermayr <
benedikt....@siemens.com>
---
drivers/watchdog/amdfch_wdt.c | 12 ++++++------
drivers/watchdog/atom-quark.c | 8 ++++----
drivers/watchdog/eiois200_wdt.c | 16 ++++++++--------
drivers/watchdog/i6300esb.c | 4 ++--
drivers/watchdog/ipc4x7e_wdt.c | 10 +++++-----
drivers/watchdog/itco.c | 6 +++---
6 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/watchdog/amdfch_wdt.c b/drivers/watchdog/amdfch_wdt.c
index 2b4db041d2a2..057689283a18 100644
--- a/drivers/watchdog/amdfch_wdt.c
+++ b/drivers/watchdog/amdfch_wdt.c
@@ -36,17 +36,17 @@
#define AMDFCH_WDT_MEM_MAP_SIZE 0x100
#define AMDFCH_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
- #define AMDFCH_WDT_START_STOP_BIT (1 << 0)
- #define AMDFCH_WDT_FIRED_BIT (1 << 1)
- #define AMDFCH_WDT_ACTION_RESET_BIT (1 << 2)
- #define AMDFCH_WDT_DISABLE_BIT (1 << 3)
+ #define AMDFCH_WDT_START_STOP_BIT BIT(0)
+ #define AMDFCH_WDT_FIRED_BIT BIT(1)
+ #define AMDFCH_WDT_ACTION_RESET_BIT BIT(2)
+ #define AMDFCH_WDT_DISABLE_BIT BIT(3)
/* 6:4 bits Reserved */
- #define AMDFCH_WDT_TRIGGER_BIT (1 << 7)
+ #define AMDFCH_WDT_TRIGGER_BIT BIT(7)
#define AMDFCH_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
#define AMDFCH_WDT_COUNT_MASK 0xFFFF
#define AMD_PM_WATCHDOG_EN_REG 0x00
- #define AMD_PM_WATCHDOG_TIMER_EN (0x01 << 7)
+ #define AMD_PM_WATCHDOG_TIMER_EN BIT(7)
#define AMD_PM_WATCHDOG_CONFIG_REG 0x03
#define AMD_PM_WATCHDOG_32USEC_RES 0x0
diff --git a/drivers/watchdog/atom-quark.c b/drivers/watchdog/atom-quark.c
index 1191231e5078..813eab93f34c 100644
--- a/drivers/watchdog/atom-quark.c
+++ b/drivers/watchdog/atom-quark.c
@@ -23,17 +23,17 @@
#define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x095e
#define WDTBA_REG 0x84
-# define WDTBA_ENABLED (1U << 31)
+# define WDTBA_ENABLED BIT(31)
# define WDTBA_ADDRMASK 0xffc0
#define TIMER1_REG 0x00
#define TIMER2_REG 0x04
#define RELOAD0_REG 0x0c
#define CONFIG_REG 0x10
-# define CONFIG_RESET_ENABLE (1 << 4)
+# define CONFIG_RESET_ENABLE BIT(4)
#define LOCK_REG 0x18
-# define LOCK_WDT_LOCK (1 << 0)
-# define LOCK_WDT_ENABLE (1 << 1)
+# define LOCK_WDT_LOCK BIT(0)
+# define LOCK_WDT_ENABLE BIT(1)
static void unlock_timer_regs(UINT32 wdt_base)
{
diff --git a/drivers/watchdog/eiois200_wdt.c b/drivers/watchdog/eiois200_wdt.c
index b3f136942f3e..e0c3f530e6bb 100644
--- a/drivers/watchdog/eiois200_wdt.c
+++ b/drivers/watchdog/eiois200_wdt.c
@@ -36,19 +36,19 @@
#define EIOIS200_200_CHIPID 0x9610
#define EIOIS200_211_CHIPID 0x9620
#define EIOIS200_SIOCTRL 0x23
-#define EIOIS200_SIOCTRL_SIOEN (1 << 0)
-#define EIOIS200_SIOCTRL_SWRST (1 << 1)
+#define EIOIS200_SIOCTRL_SIOEN BIT(0)
+#define EIOIS200_SIOCTRL_SWRST BIT(1)
#define EIOIS200_IRQCTRL 0x70
-#define EIOIS200_PMC_STATUS_IBF (1 << 1)
-#define EIOIS200_PMC_STATUS_OBF (1 << 0)
+#define EIOIS200_PMC_STATUS_IBF BIT(1)
+#define EIOIS200_PMC_STATUS_OBF BIT(0)
#define EIOIS200_LDAR 0x30
-#define EIOIS200_LDAR_LDACT (1 << 0)
+#define EIOIS200_LDAR_LDACT BIT(0)
#define EIOIS200_IOBA0H 0x60
#define EIOIS200_IOBA0L 0x61
#define EIOIS200_IOBA1H 0x62
#define EIOIS200_IOBA1L 0x63
-#define EIOIS200_FLAG_PMC_READ (1 << 0)
+#define EIOIS200_FLAG_PMC_READ BIT(0)
#define PMC_WDT_CMD_WRITE 0x2a
#define PMC_WDT_CMD_READ 0x2b
@@ -56,8 +56,8 @@
#define PMC_WDT_MIN_TIMEOUT_MS 1000
#define PMC_WDT_MAX_TIMEOUT_MS 32767000
-#define WDT_STA_AVAILABLE (1 << 0)
-#define WDT_STA_RESET (1 << 7)
+#define WDT_STA_AVAILABLE BIT(0)
+#define WDT_STA_RESET BIT(7)
#define WDT_REG_STATUS 0x00
#define WDT_REG_CONTROL 0x02
diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c
index 50540ea0d515..b19063c0a2e1 100644
--- a/drivers/watchdog/i6300esb.c
+++ b/drivers/watchdog/i6300esb.c
@@ -20,8 +20,8 @@
#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
#define ESB_LOCK_REG 0x68
-# define ESB_LOCK_WDT_LOCK (1 << 0)
-# define ESB_LOCK_WDT_ENABLE (1 << 1)
+# define ESB_LOCK_WDT_LOCK BIT(0)
+# define ESB_LOCK_WDT_ENABLE BIT(1)
#define ESB_TIMER1_REG 0x00
#define ESB_TIMER2_REG 0x04
diff --git a/drivers/watchdog/ipc4x7e_wdt.c b/drivers/watchdog/ipc4x7e_wdt.c
index af478ffe75af..c09ddc889fe7 100644
--- a/drivers/watchdog/ipc4x7e_wdt.c
+++ b/drivers/watchdog/ipc4x7e_wdt.c
@@ -24,10 +24,10 @@
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_LPC 0xa150
#define SIMATIC_WD_ENABLE_REG 0x62
-#define SIMATIC_WD_ENABLE (1 << 0)
-#define SIMATIC_WD_MACRO_MOD (1 << 1)
+#define SIMATIC_WD_ENABLE BIT(0)
+#define SIMATIC_WD_MACRO_MOD BIT(1)
#define SIMATIC_WD_SCALER_SHIFT 3
-#define SIMATIC_WD_TRIGGERED (1 << 7)
+#define SIMATIC_WD_TRIGGERED BIT(7)
#define SIMATIC_WD_TRIGGER_REG 0x66
#define SUNRISEPOINT_H_MMCFG_BASE 0xf0000000
@@ -36,13 +36,13 @@
#define P2SB_SBREG_BAR 0x10
#define P2SB_SBREG_BARH 0x14
#define P2SB_CTRL 0xe0
-#define P2SB_CFG_HIDE (1 << 8)
+#define P2SB_CFG_HIDE BIT(8)
#define GPIO_COMMUNITY0_PORT_ID 0xaf
/* drives SAFE_EN_N */
#define PAD_CFG_DW0_GPP_A_23 0x4b8
-#define PAD_CFG_GPIOTXSTATE (1 << 0)
+#define PAD_CFG_GPIOTXSTATE BIT(0)
static UINTN mmcfg_address(UINTN bus, UINTN device, UINTN function,
UINTN offset)
diff --git a/drivers/watchdog/itco.c b/drivers/watchdog/itco.c
index 04e38be5186e..ccd3dfe5c871 100644
--- a/drivers/watchdog/itco.c
+++ b/drivers/watchdog/itco.c
@@ -21,11 +21,11 @@
#include "utils.h"
#define SMI_EN_REG 0x30
-#define TCO_EN (1 << 13)
-#define GBL_SMI_EN (1 << 0)
+#define TCO_EN BIT(13)
+#define GBL_SMI_EN BIT(0)
#define TCO_RLD_REG 0x00
-#define TCO1_CNT_NO_REBOOT (1 << 0)
+#define TCO1_CNT_NO_REBOOT BIT(0)
#define TCO1_CNT_REG 0x08
#define TCO_TMR_HLT_MASK (1 << 11)
#define TCO_TMR_REG 0x12
--
2.34.1