I was trying to synthesize a basic design to gates using Yosys and the option for the ABC cell library. Run when I run, I get the following error. I tried to send an email a while back but got no response? Any chance this can be corrected?
11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
ERROR: Can't open liberty file `/yosys-yosys-0.9/examples/cmos/cmos_cells.lib': No such file or directory
Finding SVG file...
No *.svg file found. Diagram will not open.
Done
Thanks