Print statements not working in files other than testbench.sv

[Trupti Rao]

Hey!

I have just started learning System Verilog, I was doing one of the labs when I realised that statements like "assert" and "$display" do not print anything in the log file if they are not a part of the design.sv or tentbench.sv . Is there any way to let the "assert" or "$display" statements in other attached files print in the log file?

What I discovered was purely based on a lot of trial and errors, so kindly let me know if I have misunderstood anything. 

The link to my code:

https://www.edaplayground.com/x/wFBp

This design compiles and simulates in Questa using the run.do script.

Thanks,

Trupti Rao

[EDA Playground]

I have corrected various things. Have a look at : https://www.edaplayground.com/x/EXiG .

For example, the run.do file is just for runtime simulator commands on EDA Playground, not for compiling. I have put your testbench in testbench.sv and your design in design.sv and deleted all the other tabs.

You don't want a sensitivity list in your clock generator - that just locks it.

You do want a delay (I imagine) in the loop that generates the input stimulus.

You need a call to $finish (or $stop) to stop your simulation, because your clock generator loop will run forever.

Matthew

[Trupti Rao]

Hey!

Thank you! That helped me understand better. Now I know that I didn't need the run.do file at all!

I also had a question of how to make an attached file behave like a testbench. I realized the answer to that is just to add the attached files and type:

`include "top.sv"

in the testbench.sv provided by default in the playground. I got to know of this solution from a friend and (though as basic as it sounds) I am going to leave it here for anyone in search of the same.

Thank you!

Trupti Rao